Semiconductor device and method of manufacturing the same

• US 9,419,013 B1
• Filed: 12/02/2015
• Issued: 08/16/2016
• Est. Priority Date: 10/08/2015
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Dong Sik, Lee, Woong Seop, Baek, Seok Cheon, Lee, Byung Jin
• Primary Examiner(s): Potter, Roy
• Assistant Examiner(s): Patton, Paul
• Application Number:
  US14/956,539
• Time in Patent Office: 258 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 23/535 including internal interconnections, e.g. cross-under constructions internal lead connections H01L23/481
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 43/50 characterised by the boundary region between the core and peripheral circuit regions

Abstract

A semiconductor device, including gate electrodes perpendicularly stacked on a substrate; channel holes extending perpendicularly to the substrate, the channel holes penetrating through the gate electrodes, the channel holes having a channel region; gate pads extended from the gate electrodes by different lengths; and contact plugs connected to the gate pads, at least a portion of the gate pads having a region having a thickness less than a thickness of the gate electrode connected to the at least a portion of the gate pads.

Claims

1. A semiconductor device, comprising:

gate electrodes perpendicularly stacked on a substrate;

channel holes extending perpendicularly to the substrate, the channel holes penetrating through the gate electrodes, the channel holes having a channel region;

gate pads extended from the gate electrodes by different lengths; and

contact plugs connected to the gate pads,

at least a portion of the gate pads having a region having a thickness less than a thickness of the gate electrode connected to the at least a portion of the gate pads.

2. The semiconductor device as claimed in claim 1, wherein:

the gate pads include contact regions in which lower gate pads extend further than upper gate pads connected to the contact plugs, and

a thickness of the gate pad in the contact region is less than a thickness of the gate electrode.

3. The semiconductor device as claimed in claim 2, wherein the gate pads have thicknesses less than thicknesses of the gate electrodes in an entirety of the contact regions.

4. The semiconductor device as claimed in claim 2, wherein the gate pads have thicknesses continuously and gradually reduced in the contact regions.

5. The semiconductor device as claimed in claim 2, wherein each of the gate pads has a curved portion in which a thickness of the gate pad is discontinuously and rapidly reduced in a vicinity of the contact region, each of the gate pads extending horizontally in a region except for the curved portion.

6. The semiconductor device as claimed in claim 1, wherein a difference in thicknesses between the gate pads and the gate electrodes connected to the gate pads is different in each of the gate pads.

7. The semiconductor device as claimed in claim 6, wherein the difference in thicknesses in the gate pads is increased in an upward direction from an upper surface of the substrate.

8. The semiconductor device as claimed in claim 6, wherein the difference in thicknesses in the gate pads is increased in an upward direction from an upper surface of the substrate among group units including two or more of the gate pads.

9. The semiconductor device as claimed in claim 1, further comprising an etch-stop layer on the gate pads,

wherein the contact plugs penetrate through the etch-stop layer.

10. The semiconductor device as claimed in claim 9, wherein the etch-stop layer is in contact with the gate pads.

11. A semiconductor device, comprising:

gate electrodes stacked perpendicularly on a substrate;

gate pads having contact regions, the gate pads extending from the gate electrodes by different lengths; and

contact plugs connected to the gate pads in the contact regions,

at least a portion of the gate pads having a reduced thickness in the contact regions.

12. The semiconductor device as claimed in claim 11, wherein the contact regions include regions in which a lower gate pad among the gate pads extends further than an upper gate pad among the gate pads.

13. The semiconductor device as claimed in claim 11, wherein each of the gate pads has a step portion or a curved portion such that each of the gate pads has the reduced thickness in the contact regions.

14. The semiconductor device as claimed in claim 11, wherein a difference in thicknesses of the gate electrode and the gate pad connected to the gate electrode is in a range of about 5 Å

to about 100 Å

.

15. The semiconductor device as claimed in claim 11, wherein a degree of reduction in thicknesses of the gate pads is in proportion to or in inverse proportion to a distance between the gate pads and the substrate.