Displays with intra-frame pause

• US 9,424,793 B2
• Filed: 05/29/2015
• Issued: 08/23/2016
• Est. Priority Date: 02/04/2014
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Kitsomboonloha, Rungrot, Park, Kwang Soon, Lin, Chin-Wei, Huang, Chun-Yao, Chang, Shih Chang, Lee, Szu-Hsien
• Primary Examiner(s): BACHNER, ROBERT G
• Application Number:
  US14/726,312
• Publication Number:
  US 20150269897A1
• Time in Patent Office: 452 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 3/0412 Digitisers structurally integrated in a display
• CPC Class Codes: G06F 3/0416 Control or interface arrangements specially adapted for digitisers
• CPC Class Codes: G06F 3/04166 Details of scanning methods, e.g. sampling time, grouping of sub areas or time sharing with display driving Synchronisation with the driving of the display or the backlighting unit to avoid interferences generated internally G06F3/04184
• CPC Class Codes: G06F 3/04184 Synchronisation with the driving of the display or the backlighting unit to avoid interferences generated internally
• CPC Class Codes: G06F 3/0443 using a single layer of sensing electrodes
• CPC Class Codes: G09G 2300/0408 Integration of the drivers onto the display substrate
• CPC Class Codes: G09G 2300/0842 forming a memory circuit, e.g. a dynamic memory with one capacitor
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence

Abstract

A touch screen display may include gate line driver circuitry coupled to a display pixel array. The display may be provided with intra-frame pausing (IFP) capabilities, where touch or other operations may be performed during one or more intra-frame blanking intervals. In one suitable arrangement, a gate driver circuit may include multiple gate line driver segments each of which is activated by a separate gate start pulse. Each gate start pulse may only be released at the end of an IFP interval. In another suitable arrangement, dummy gate driver units may be interposed among active gate driver units. Gate output signals may propagate through the dummy gate driver units during the IFP internal. In another suitable arrangement, each active gate driver unit may be provided with a buffer portion that protects at least some transistor in the gate driver unit from undesired stress.

Claims

1. An electronic device, comprising:

an array of display pixels arranged in rows and columns; and

gate driver circuitry coupled to the array of display pixels, wherein operation of the gate driver circuitry is temporarily suspended during an intra-frame blanking interval that occurs between loading data into a first row of the array and loading data into a last row of the array, wherein the gate driver circuitry includes a gate driver unit having an output on which a corresponding gate line output signal is provided to display pixels arranged along a corresponding row in the array, and wherein the gate driver unit comprises;

a transistor having a source-drain terminal that is coupled to the output of the gate driver unit and having a gate terminal; and

a pull-down circuit that is coupled to the gate terminal of the transistor and that is turned on during the entirety of the intra-frame blanking interval.

2. The electronic device defined in claim 1, wherein the gate driver unit directly receives a gate line output signal from a non-adjacent gate driver unit in the chain.

3. The electronic device defined in claim 1, wherein the gate driver unit directly receives gate line output signals from at least two different non-adjacent gate driver units in the chain.

4. The electronic device defined in claim 1, wherein the gate driver unit is controlled using two clock signals with different phases.

5. An electronic device, comprising:

an array of display pixels arranged in rows and columns; and

gate driver circuitry coupled to the array of display pixels, wherein operation of the gate driver circuitry is temporarily suspended during an intra-frame blanking interval, wherein the gate driver circuitry includes a gate driver unit having an output on which a corresponding gate line output signal is provided to display pixels arranged along a corresponding row in the array, and wherein the gate driver unit comprises;

a transistor having a source-drain terminal that is coupled to the output of the gate driver unit and having a gate terminal; and

a pull-down circuit that is coupled to the gate terminal of the transistor and that is turned on during the entirety of the intra-frame blanking interval, wherein the gate driver unit comprises one gate driver unit in a chain of gate driver units in the gate driver circuitry, and wherein the gate driver unit further comprises;

memory circuitry for buffering gate line output signals from at least one preceding gate driver unit in the chain.

6. The electronic device defined in claim 5, wherein the memory circuitry comprises a storage capacitor having a terminal that is connected to a power supply terminal.

7. The electronic device defined in claim 6, wherein the memory circuitry further comprises:

a first transistor having a source-drain terminal that is coupled to the gate terminal of the transistor and having a gate terminal; and

a second transistor having a first source-drain terminal that is coupled to another terminal of the storage capacitor and a second source-drain terminal that is coupled to the gate terminal of the first transistor.