Data storage device

• US 9,424,898 B2
• Filed: 10/10/2014
• Issued: 08/23/2016
• Est. Priority Date: 07/02/2014
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: Chun, Dong Yeob, An, Joong Hyun, Kim, Kwang Hyun
• Primary Examiner(s): Lappas, Jason
• Application Number:
  US14/512,126
• Publication Number:
  US 20160005444A1
• Time in Patent Office: 683 Days
• Field of Search: 365/233.15, 365/233.17, 365/229
• US Class Current: 1/1
• CPC Class Codes: G06F 3/0617 in relation to availability
• CPC Class Codes: G06F 3/0653 Monitoring storage devices or systems
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 16/32 Timing circuits
• CPC Class Codes: G11C 2207/2227 Standby or low power modes
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management

Abstract

A data storage device includes a first memory device suitable for performing an internal operation in response to a first internal operation command; and a state checking block suitable for performing a state read operation by transmitting a state read command one or more times to the first memory device during one of an initial mode and a repeat mode which is set based on a type of the internal operation.

Claims

1. A data storage device comprising:

a first memory device suitable for performing an internal operation in response to a first internal operation command; and

a state checking block suitable for performing a state read operation by transmitting a state read command one or more times to the first memory device during one of an initial mode and a repeat mode which is set based on a type of the internal operation,

wherein the state checking block sets an initial standby time during the initial mode based on an expected performance time of the internal operation, and transmits an initial state read command to the first memory device when the initial standby time passes.

2. The data storage device according to claim 1,

wherein the first memory device outputs initial response data in response to the initial state read command, and

wherein the state checking block determines whether the internal operation is completed based on the initial response data, and ends the state read operation or enters the repeat mode according to a determination result.

3. The data storage device according to claim 2, wherein the state checking block sets a repeat standby time during the repeat mode based on the expected performance time of the internal operation when it is determined that the internal operation is not completed, and transmits a repeat state read command to the first memory device when the repeat standby time passes.

4. The data storage device according to claim 3,

wherein the first memory device outputs repeat response data in response to the repeat state read command, and

wherein the state checking block determines whether the internal operation is completed based on the repeat response data, and ends the state read operation or retains the repeat mode according to a determination result.

5. The data storage device according to claim 4, wherein the state checking block repeatedly transmits the repeat state read command each time the repeat standby time passes when retaining the repeat mode.

6. The data storage device according to claim 1, wherein the state checking block ends the state read operation when the state read operation is performed for a preset time or when the number of transmission times of the state read command reaches a preset number of times during the repeat mode.

7. The data storage device according to claim 1, further comprising:

a processor configured to transmit the first internal operation command to the first memory device, and transmit information on the type of the internal operation to the state checking block.

8. The data storage device according to claim 7, wherein the state checking block outputs a permission request signal to the processor and receives a permission signal from the processor before transmitting the state read command.

9. The data storage device according to claim 1, wherein the state checking block reports to the processor whether a result of the internal operation is a success or a failure or if a time-out occurs in the first memory device when ending the state read operation.

10. The data storage device according to claim 1, further comprising a second memory device,

wherein the processor transmits a second internal operation command to the second memory device after transmitting the first internal operation command, and

wherein the state checking block performs state checking operations for the respective first and second memory devices.

11. The data storage device according to claim 10, wherein the state checking block transmits the state read command to the second memory device when it is determined that the internal operation of the first memory device is completed.

12. The data storage device according to claim 10, wherein the state checking block transmits the state read command to the second memory device regardless of whether the internal operation of the first memory device is completed.

13. A data storage device comprising:

a first memory device suitable for performing an internal operation in response to a first internal operation command;

a state checking block suitable for performing a state read operation by transmitting a state read command one or more times to the first memory device during one of an initial mode and a repeat mode, and

a processor configured to transmit the first internal operation command to the first memory device, and transmit information on a type of the internal operation to the state checking block;

wherein the state checking block transmits the state read command based on an initial standby time of the initial mode and a repeat standby time of the repeat mode which are set based on the type of the internal operation.

14. The data storage device according to claim 13, wherein the state checking block sets the initial standby time during the initial mode based on an expected performance time of the internal operation, and transmits an initial state read command to the first memory device when the initial standby time passes.

15. The data storage device according to claim 14,

wherein the first memory device outputs initial response data in response to the initial state read command, and

wherein the state checking block determines whether the internal operation is completed based on the initial response data, and ends the state read operation or enters the repeat mode according to a determination result.

16. The data storage device according to claim 15, wherein the state checking block sets the repeat standby time during the repeat mode based on the expected performance time of the internal operation when it is determined that the internal operation is not completed, and transmits a repeat state read command to the first memory device when the repeat standby time passes.

17. The data storage device according to claim 16,

wherein the first memory device outputs repeat response data in response to the repeat state read command, and

wherein the state checking block determines whether the internal operation is completed based on the repeat response data, and ends the state read operation or retains the repeat mode according to a determination result.

18. The data storage device according to claim 17, wherein the state checking block repeatedly transmits the repeat state read command each time the repeat standby time passes when retaining the repeat mode.

19. The data storage device according to claim 13, wherein the state checking block ends the state read operation when the state read operation is performed for a preset time or when the number of transmission times of the state read command reaches a preset number of times during the repeat mode.