Division operations for memory

• US 9,430,191 B2
• Filed: 11/08/2013
• Issued: 08/30/2016
• Est. Priority Date: 11/08/2013
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Wheeler, Kyle B.
• Primary Examiner(s): Malzahn, David H
• Application Number:
  US14/075,539
• Publication Number:
  US 20150134713A1
• Time in Patent Office: 1,026 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G06F 2207/5353 Restoring division
• CPC Class Codes: G06F 5/01 for shifting, e.g. justifying, scaling, normalising digital stores in which the information is moved stepwise, e.g. shift-registers G11C19/00; digital stores in which the information circulates G11C21/00
• CPC Class Codes: G06F 7/535 Dividing only

Abstract

Examples of the present disclosure provide apparatuses and methods for performing division operations in a memory. An example apparatus comprises a first address space comprising a first number of memory cells coupled to a sense line and to a first number of select lines wherein the first address space stores a dividend value. A second address space comprises a second number of memory cells coupled to the sense line and to a second number of select lines wherein the second address space stores a divisor value. A third address space comprises a third number of memory cells coupled to the sense line and to a third number of select lines wherein the third address space stores a remainder value. Sensing circuitry can be configured to receive the dividend value and the divisor value, divide the dividend value by the divisor value, and store a remainder result in the third number of memory cells.

Claims

1. A method for performing division operations comprising:

performing a division operation using a logical representation of a dividend value stored in a first portion of N number of memory cells coupled to a sense line of a memory array and a logical representation of a divisor value stored in a second portion of the number of memory cells coupled to the sense line of the memory array;

storing a logical representation of a quotient value of a result of the division operation in a third portion of the number of memory cells coupled to the sense line of the memory array;

copying a bit stored in the Nth memory cell of the first portion of the number of memory cells into a first memory cell of a fourth portion of the number of memory cells, wherein the fourth portion of the number of memory cells stores a logical representation of a remainder value of the result of the division operation; and

comparing the divisor value with the remainder value.

2. The method of claim 1, further comprising storing the logical representation of the dividend value as a bit-vector in the first portion of the number of memory cells coupled to the sense line wherein each memory cell in the first portion of the number of memory cells stores a respective bit from the bit-vector.

3. The method of claim 1, further comprising storing the logical representation of the divisor value as a bit-vector in the second portion of the number of memory cells coupled to the sense line wherein each memory cell in the second portion of the number of memory cells stores a respective bit from the bit-vector.

4. The method of claim 1, wherein storing the logical representation of the quotient value comprises storing the logical representation of the quotient value as a bit-vector in the third portion of the number of memory cells coupled to the sense line wherein each memory cell in the third portion of the number of memory cells stores a respective bit from the bit-vector.

5. The method of claim 1, wherein the quotient value is an integer representing a number of times that the divisor value wholly divides the dividend value.

6. The method of claim 1, further comprising, if the divisor value is less than or equal to the remainder value:

subtracting the divisor value from the remainder value and storing a logical representation of a resulting value as the logical representation of the remainder value in the fourth portion of the number of memory cells;

shifting and incrementing the logical representation of the quotient value to update the quotient value; and

shifting the logical representation of the remainder value to update the remainder value.

7. The method of claim 6, further comprising, if the divisor value is greater than the remainder value:

shifting the logical representation of the quotient value to update the quotient value; and

shifting the logical representation of the remainder value to update the remainder value.

8. The method of claim 7, further comprising:

copying a bit stored in Nth-1 memory cell of the first portion of the number of memory cells into the first memory cell of the fourth portion of the number of memory cells; and

comparing the divisor value with the remainder value.

9. The method of claim 8, further comprising initializing the remainder value and the quotient value to zero before copying the bit stored in the Nth memory cell of the first portion of the number of memory cells into the first memory cell of the fourth portion of the number of memory cells.

10. The method of claim 7, further comprising creating a mask responsive to the comparison, wherein the mask indicates whether the divisor value is less than or equal to the remainder value or whether the divisor value is greater than the remainder value.

11. An apparatus comprising:

a first address space of a memory array comprising a first number of memory cells coupled to a sense line and to a first number of select lines,. wherein the first address space is configured to store a dividend value;

a second address space of the memory array comprising a second number of memory cells coupled to the sense line and to a second number of select lines, wherein the second address space is configured to store a divisor value;

a third address space of the memory array comprising a third number of memory cells coupled to the sense line and to a third number of select lines, wherein the third address space is configured to store a remainder value; and

a controller coupled to the memory array and configured to control;

sensing circuitry to;

receive the dividend value and the divisor value; and

divide the dividend value by the divisor value; and

storing of the remainder value in the third address space;

wherein the sensing circuitry comprises transistors formed on pitch with the memory cells of the memory array.

12. The apparatus of claim 11, wherein the first number of memory cells coupled to the sense line comprises N memory cells coupled to the sense line and wherein the sensing circuitry being controllable to divide the dividend value by the divisor value comprises the sensing circuitry being controllable to:

copy a bit stored in the Nth memory cell of the first number of memory cells into a first memory cell of the third number of memory cells; and

compare the divisor value with the remainder value.

13. The apparatus of claim 12, wherein the controller being configured to control storing of the remainder value in the third address space comprises the controller being configured to control the sensing circuitry to:

if the divisor value is less than or equal to the remainder value;

subtract the divisor value from the remainder value and store a logical representation of a resulting value in the third number of memory cells; and

shift the logical representation of the resulting value to update the remainder value,

wherein the sensing circuitry being controllable to divide the dividend value by the divisor value further comprises the sensing circuitry being controllable to shift and increment a logical representation of a quotient value stored in a fourth address space of the memory array.

14. The apparatus of claim 13, wherein the sensing circuitry being controllable to divide the dividend value by the divisor value further comprises the sensing circuitry being controllable to shift the logical representation of the quotient value to update the quotient value if the divisor value is greater than the remainder value.

15. The apparatus of claim 14, wherein the controller being configured to control storing of the remainder value in the third address space comprises the controller configured to control the sensing circuitry to shift a logical representation of the remainder value to update the remainder value if the divisor value is greater than the remainder value.

16. The apparatus of claim 15, wherein the sensing circuitry being controllable to divide the dividend value by the divisor value further comprises the sensing circuitry being controllable to create a mask responsive to the comparison, wherein the mask indicates whether the divisor value is less than or equal to the remainder value or whether the divisor value is greater than the remainder value.

17. The apparatus of claim 11, further comprising a fourth address space of the memory array comprising a fourth number of memory cells coupled to the sense line and to a fourth number of select lines,. wherein the controller is configured to control storing of a quotient value in the fourth number of memory cells.

18. The apparatus of claim 11, wherein the sensing circuitry is controllable to divide the dividend value by the divisor value without transferring data via a sense line address access.

19. The apparatus of claim 11, wherein the sensing circuitry comprises a compute component including transistors that are on pitch with the first number of memory cells, the second number of memory cells, and the third number of memory cells.

20. A method for performing a number of division operations comprising:

dividing a number of dividend values stored in a number of first portions of memory cells coupled to a number of sense lines of a memory array by a number of divisor values stored in a number of second portions of the memory cell coupled to the number of sense lines of the memory array, wherein;

each of the number of first portions of the memory cells is coupled to a different sense line of the number of sense lines and wherein each of the number of dividend values is stored in a different first portion of the number of first portions; and

each of the number of second portions of the memory cells is coupled to a different sense line of the number of sense lines and wherein each of the number of divisor values is stored in a different second portion of the number of second portions;

storing a number of quotient values of a result of dividing the number of dividend values by the number of divisor values in a number of third portions of the memory cells coupled to the number of sense lines of the memory array; and

storing a number of remainder values of the result of the number of dividing the number of dividend values by the number of divisor values in a fourth portion of the memory cells coupled to the number of sense lines of the memory array;

wherein;

a number of computations used to perform the number of division operations is the same as a number of computations used to perform any one of the number of division operations;

each of the number of division operations comprises a respective dividend value from the number of dividend values being divided by a respective divisor value from the number of divisor values wherein the dividend value and the divisor value of a respective division operation of the number of division operations are stored in memory cells coupled to the same sense line of the number of sense lines; and

each of the number of first portions of memory cells coupled to a number of sense lines comprises N memory cells coupled to one of the number of sense lines;

wherein;

dividing the number of dividend values by the number of divisor values comprises copying each bit stored in the Nth memory cells of the first portions of the number of memory cells into each of a first memory cells of the fourth portions of the number of memory cells; and

a number of computations involved in copying each bit stored in the Nth memory cell of the first portions of the number of memory cells does not change regardless of a size of the number of dividend values, the number of divisor values, and the number of remainder values.

21. The method of claim 20, wherein dividing the number of dividend values by the number of divisor values comprises comparing the number of divisor values with the number of remainder values.

22. The method of claim 21, further comprising, for each of the divisor values that is less than or equal to a corresponding remainder value from the number of remainder values:

subtracting a divisor value from the corresponding remainder value and storing a logical representation of a resulting value as a logical representation of the corresponding remainder value in a corresponding fourth portion of the number of memory cells;

shifting and incrementing a logical representation of a corresponding quotient value to update the corresponding quotient value;

shifting the logical representation of the corresponding remainder value to update the corresponding remainder value.

23. The method of claim 22, further comprising:

for each of the divisor values that is greater than a corresponding remainder value from the number of remainder values;

shifting the logical representation of the corresponding quotient value to update the corresponding quotient value; and

shifting the logical representation of the corresponding remainder value to update the corresponding remainder value.

24. The method of claim 23, further comprising:

copying each bit stored in the Nth-1 memory cells of the first portions of the number of memory cells into each of the first memory cells of the fourth portions of the number of memory cells; and

comparing the number of divisor values with the number of remainder values.

25. The method of claim 24, further comprising initializing the number of remainder values and the number of quotient values to zero before copying each bit stored in the Nth memory cells of the first portions of the number of memory cells into the first memory cells of the fourth portions of the number of memory cells.

26. An apparatus comprising:

a first address space of a memory array comprising a first number of memory cells coupled to a sense line and to a first number of select lines wherein the first address space is configured to store a dividend value;

a second address space of the memory array comprising a second number of memory cells coupled to the sense line and to a second number of select lines wherein the second address space is configured to store a divisor value;

a third address space of the memory array comprising a third number of memory cells coupled to the sense line and to a third number of select lines wherein the third address space is configured to store a remainder value; and

a controller coupled to the memory array and configured to control;

sensing circuitry to;

receive the dividend value and the divisor value; and

divide the dividend value by the divisor value; and

storing the remainder value in the third address space;

wherein the first number of memory cells coupled to the sense line comprises N memory cells coupled to the sense line and wherein the sensing circuitry being controllable to divide the dividend value by the divisor value comprises the sensing circuitry being controllable to;

copy a bit stored in the Nth memory cell of the first number of memory cells into a first memory cell of the third number of memory cells; and

compare the divisor value with the remainder value.

27. An apparatus comprising:

a first address space of a memory array comprising a first number of memory cells coupled to a sense line and to a first number of select lines wherein the first address space is configured to store a dividend value;

a second address space of the memory array comprising a second number of memory cells coupled to the sense line and to a second number of select lines wherein the second address space is configured to store a divisor value;

a third address space of the memory array comprising a third number of memory cells coupled to the sense line and to a third number of select lines wherein the third address space is configured to store a remainder value; and

a controller coupled to the memory array and configured to control;

sensing circuitry configured to;

receive the dividend value and the divisor value; and

divide the dividend value by the divisor value; and

storing the remainder value in the third address space;

wherein the sensing circuitry is configured to divide the dividend value by the divisor value without transferring data via a sense line address access.

28. An apparatus comprising:

a first address space of a memory array comprising a first number of memory cells coupled to a sense line and to a first number of select lines wherein the first address space is configured to store a dividend value;

a second address space of the memory array comprising a second number of memory cells coupled to the sense line and to a second number of select lines wherein the second address space is configured to store a divisor value;

a third address space of the memory array comprising a third number of memory cells coupled to the sense line and to a third number of select lines wherein the third address space is configured to store a remainder value; and

a controller coupled to the memory array and configured to control;

sensing circuitry configured to;

receive the dividend value and the divisor value;

divide the dividend value by the divisor value; and

storing the remainder value in the third address space;

wherein the sensing circuitry comprises a compute component including transistors that are on pitch with the first number of memory cells, the second number of memory cells, and the third number of memory cells.