Interface for communication between voltage domains

• US 9,431,177 B2
• Filed: 03/13/2015
• Issued: 08/30/2016
• Est. Priority Date: 05/23/2012
• Status: Active Grant

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: Steeneken, Peter Gerard
• Primary Examiner(s): Takaoka, Dean
• Assistant Examiner(s): Wong, Alan
• Application Number:
  US14/657,978
• Publication Number:
  US 20150187503A1
• Time in Patent Office: 536 Days
• Field of Search: 333/24.C, 333/109, 333/116, 333/238
• US Class Current: 1/1
• CPC Class Codes: H01G 4/06 Solid dielectrics
• CPC Class Codes: H01G 4/385 Single unit multiple capacitors, e.g. dual capacitor in one coil
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 23/48 Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
• CPC Class Codes: H01L 23/642 Capacitive arrangements H01L23/49589, H01L23/645, H01L23/647, H01L23/66 take precedence; capacitive effects between wiring layers on the semiconductor body H01L23/5222
• CPC Class Codes: H01L 25/0655 the devices being arranged next to each other
• CPC Class Codes: H01L 28/60 Electrodes
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01P 1/04 Fixed joints
• CPC Class Codes: H03H 7/004 Capacitive coupling circuits not otherwise provided for
• CPC Class Codes: H04B 5/22 Capacitive coupling

Abstract

In one or more embodiments, circuitry is provided for isolation and communication of signals between circuits operating in different voltage domains using capacitive coupling. The capacitive coupling is provided by one or more capacitive structures having a breakdown voltage that is defined by way of the various components and their spacing. The capacitive structures each include three capacitive plates arranged to have two plates located in an upper layer and one plate located in a lower layer. A communication signal can be transmitted via the capacitive coupling created between the lower plate and each of the upper plates, respectively.

Claims

1. A device, comprising:

a substrate;

a dielectric layer over the substrate;

a lower capacitor plate in the dielectric layer, wherein the lower capacitor layer is parallel to a surface of the substrate and is located at a first distance from the surface of the substrate;

two upper capacitor plates in the dielectric layer over and at a second distance from the lower capacitor plate, wherein the two upper capacitor plates combined substantially overlap the lower capacitor plate and wherein the two upper capacitor plates do not touch each other;

wherein the first distance and the second distance are preselected based on a breakdown voltage of a material of the dielectric layer.

2. The device of claim 1, wherein the lower capacitor plate and the two upper capacitor plates are configured to form two capacitors connected in series.

3. The device of claim 1, wherein the two upper capacitor plates do not touch the lower capacitor plate.

4. The device of claim 1, wherein the lower capacitor plate is configured to be connected to a power terminal.

5. The device of claim 4, wherein the two upper capacitor plates are configured to be connected to power terminals that are of opposite polarity of the power terminal that the lower capacitor plate is configured to be connected to.

6. The device of claim 1, wherein the first distance and the second distance are further preselected based on a maximum voltage for which the device is designed to be used with.

7. The device of claim 1, wherein the substrate includes a handle wafer and a silicon layer.

8. The device of claim 7, wherein a buried oxide layer is included to isolate the handle wafer from the silicon layer.

9. The device of claim 8, wherein an oxide ring protruding from the buried oxide layer isolates a portion of the silicon layer of the substrate from other portions of the silicon layer.

10. The device of claim 9, wherein the portion of the silicon layer that is isolated by the oxide ring lies immediately under the lower capacitor plate and the portion of the silicon layer is bigger in area than the area of the lower capacitor plate such that the lower capacitor plate does not protrude out of the portion of the silicon layer on a horizontal plane.

11. A communication device fabricated on a substrate, comprising:

a transmitter fabricated in a first voltage domain;

a receiver fabricated in a second voltage domain;

wherein the transmitter is separated from the receiver through a unreferenced voltage domain, wherein the receiver including a capacitive device, the device comprising;

a dielectric layer over the substrate;

a lower capacitor plate in the dielectric layer, wherein the lower capacitor layer is parallel to a surface of the substrate and is located at a first distance from the surface of the substrate;

two upper capacitor plates in the dielectric layer over and at a second distance from the lower capacitor plate, wherein the two upper capacitor plates combined substantially overlap the lower capacitor plate and wherein the two upper capacitor plates do not touch each other;

wherein the first distance and the second distance are preselected based on a breakdown voltage of a material of the dielectric layer.

12. The communication device of claim 11, wherein the lower capacitor plate and the two upper capacitor plates are configured to form two capacitors connected in series.

13. The communication device of claim 11, wherein the two upper capacitor plates do not touch the lower capacitor plate.

14. The communication device of claim 11, wherein the lower capacitor plate is configured to be connected to a power terminal.

15. The communication device of claim 14, wherein the two upper capacitor plates are configured to be connected to power terminals that are of opposite polarity of the power terminal that the lower capacitor plate is configured to be connected to.

16. The communication device of claim 11, wherein the first distance and the second distance are further preselected based on a maximum voltage for which the device is designed to be used with.

17. The communication device of claim 11, wherein the substrate includes a handle wafer and a silicon layer.

18. The communication device of claim 17, wherein a buried oxide layer is included to isolate the handle wafer from the silicon layer.

19. The communication device of claim 18, wherein an oxide ring protruding from the buried oxide layer isolates a portion of the silicon layer of the substrate from other portions of the silicon layer.

20. The communication device of claim 19, wherein the portion of the silicon layer that is isolated by the oxide ring lies immediately under the lower capacitor plate and the portion of the silicon layer is bigger in area than the area of the lower capacitor plate such that the lower capacitor plate does not protrude out of the portion of the silicon layer on a horizontal plane.