Semiconductor device, solid-state imaging device and electronic apparatus

• US 9,431,450 B2
• Filed: 10/10/2013
• Issued: 08/30/2016
• Est. Priority Date: 10/18/2012
• Status: Active Grant

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Umebayashi, Taku, Tatani, Keiji, Inoue, Hajime, Kanamura, Ryuichi
• Primary Examiner(s): Nguyen, Dao H
• Application Number:
  US14/434,288
• Publication Number:
  US 20150270307A1
• Time in Patent Office: 1,055 Days
• Field of Search: 257/292, 257/432, 257/443, 257/446, 257/459, 257/460, 257/E27.13, 257/E27.132, 257/E27.133, 257/E27.134, 257/E31.113, 257/E31.127, 257/E31.128, 257/E21.499, 257/E21.521, 257/E21.585, 438/64, 438/66, 438/652, 438/666
• US Class Current: 1/1
• CPC Class Codes: H01L 27/14612 involving a transistor
• CPC Class Codes: H01L 27/14621 Colour filter arrangements
• CPC Class Codes: H01L 27/14623 Optical shielding
• CPC Class Codes: H01L 27/14627 Microlenses
• CPC Class Codes: H01L 27/14634 Assemblies, i.e. Hybrid structures
• CPC Class Codes: H01L 27/14636 Interconnect structures
• CPC Class Codes: H01L 27/1464 Back illuminated imager structures
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 27/14645 Colour imagers
• CPC Class Codes: H01L 27/1469 Assemblies, i.e. hybrid integration

Abstract

A semiconductor device including a first semiconductor section including a first wiring layer at one side thereof, the first semiconductor section further including a photodiode, a second semiconductor section including a second wiring layer at one side thereof, the first and second semiconductor sections being secured together, a third semiconductor section including a third wiring layer at one side thereof, the second and the third semiconductor sections being secured together such the first semiconductor section, second semiconductor section, and the third semiconductor section are stacked together, and a first conductive material electrically connecting at least two of (i) the first wiring layer, (ii) the second wiring layer, and (iii) the third wiring layer such that the electrically connected wiring layers are in electrical communication.

Claims

1. A semiconductor device comprising:

a first semiconductor section including a first multilayer wiring layer at one side thereof, the first semiconductor section further including a photodiode;

a second semiconductor section including a second multilayer wiring layer at one side thereof, the first and second semiconductor sections being secured together;

a third semiconductor section including a third multilayer wiring layer at one side thereof, the second and the third semiconductor sections being secured together such that the first semiconductor section, second semiconductor section, and the third semiconductor section are stacked together;

a first contact connecting a first wiring layer of the first multilayer wiring layer and a conductive material disposed in a film of the second semiconductor section, the film of the second semiconductor section disposed at a side of the second semiconductor section that is opposite to the side at which the second multilayer wiring layer is disposed, wherein the first contact includes;

a first through hole portion penetrating a portion of the first semiconductor section in a vertical direction, wherein a conductive material embedded in the first through hole portion contacts the first wiring layer of the first multilayer wiring layer,

a second through hole portion penetrating a portion of the first semiconductor section and the first multilayer wiring layer in the vertical direction, wherein a conductive material embedded in the second through hole portion contacts the conductive material disposed in the film of the second semiconductor section, and

a first connection portion including a conductive material that connects the conductive material embedded in the first through hole portion and the conductive material embedded in the second through hole portion, wherein the first connection portion is above the first multilayer wiring layer in the vertical direction; and

a second contact connecting a second wiring layer of the second multilayer wiring layer and a third wiring layer of the third multilayer wiring layer, wherein the second contact includes;

a third through hole portion penetrating a portion of the second semiconductor section in the vertical direction, wherein a conductive material embedded in the third through hole portion contacts the second wiring layer of the second multilayer wiring layer, and

a fourth through hole portion penetrating a portion of the second semiconductor section, the second multilayer wiring layer, and a portion of the third multilayer wiring layer in the vertical direction, wherein a conductive material embedded in the fourth through hole portion contacts the third wiring layer of the third multilayer wiring layer, and wherein the conductive material disposed in the film of the second semiconductor section connects the conductive material embedded in the third through hole portion and the conductive material embedded in the fourth through hole portion.

2. The semiconductor device of claim 1, wherein the first semiconductor section, the second semiconductor section, and the third semiconductor section are stacked together in a manner such that the second multilayer wiring layer faces the third multilayer wiring layer.

3. The semiconductor device of claim 1, further comprising a pad electrode for external connection.

4. The semiconductor device of claim 3, wherein the pad electrode is disposed such that light is blocked from one or more transistors residing in the second semiconductor section.

5. The semiconductor device of claim 1, wherein the first semiconductor section comprises a sensor circuit, at least one of the second semiconductor section or the third semiconductor section comprises a logical circuit, and at least one of the second semiconductor section or the third semiconductor section comprises a memory circuit.

6. The semiconductor device of claim 1, wherein the conductive material embedded in the fourth through hole portion contacts a pad of the third wiring layer of the third multilayer wiring layer.

7. The semiconductor device of claim 1, wherein the first connection portion is disposed such that light is blocked from one or more transistors residing in the second semiconductor section.

8. The semiconductor device of claim 1, wherein the film is an interlayer insulating film disposed between the first and second semiconductor sections.

9. A backside illumination type imaging device comprising:

a first semiconductor section including a first multilayer wiring layer at one side thereof, the first semiconductor section further including a circuit region and a pixel region;

a second semiconductor section including a second multilayer wiring layer at one side thereof, the first and second semiconductor sections being secured together;

a third semiconductor section including a third multilayer wiring layer at one side thereof, the second and the third semiconductor sections being secured together such that the first semiconductor section, second semiconductor section, and the third semiconductor section are stacked together; and

a first contact connecting a first wiring layer of the first multilayer wiring layer and, a conductive material disposed in a film of the second semiconductor section, the film of the second semiconductor section disposed at a side of the second semiconductor section that is opposite to the side at which the second multilayer wiring layer is disposed, wherein the first contact includes;

a first through hole portion penetrating a portion of the first semiconductor section in a vertical direction, wherein a conductive material embedded in the first through hole portion contacts the first wiring layer of the first multilayer wiring layer,

a second through hole portion penetrating a portion of the first semiconductor section and the first multilayer wiring layer in the vertical direction, wherein a conductive material embedded in the second through hole portion contacts the conductive material disposed in the film of the second semiconductor section, and

a first connection portion including a conductive material that connects the conductive material embedded in the first through hole portion and the conductive material embedded in the second through hole portion, wherein the first connection portion is above the first multilayer wiring layer in the vertical direction; and

a second contact connecting a second wiring layer of the second multilayer wiring layer and a third wiring layer of the third multilayer wiring layer, wherein the second contact includes;

a third through hole portion penetrating a portion of the second semiconductor section in the vertical direction, wherein a conductive material embedded in the third through hole portion contacts the second wiring layer of the second multilayer wiring layer, and

a fourth through hole portion penetrating a portion of the second semiconductor section, the second multilayer wiring layer, and a portion of the third multilayer wiring layer in the vertical direction, wherein a conductive material embedded in the fourth through hole portion contacts the third wiring layer of the third multilayer wiring layer, and wherein the conductive material disposed in the film of the second semiconductor section connects the conductive material embedded in the third through hole portion and the conductive material embedded in the fourth through hole portion.

10. The imaging device of claim 9, wherein the first semiconductor section, the second semiconductor section, and the third semiconductor section are stacked together in a manner such that the second multilayer wiring layer faces the third multilayer wiring layer.

11. The solid state imaging device of claim 9, further comprising a pad electrode for external connection.

12. The imaging device of claim 11, wherein the pad electrode is disposed below the pixel region such that light is blocked from one or more transistors residing in the second semiconductor section.

13. The imaging device of claim 9, wherein the film is an interlayer insulating film disposed between the first and second semiconductor sections.

14. The imaging device of claim 9, wherein the first semiconductor section comprises a sensor circuit, at least one of the second semiconductor section or the third semiconductor section comprises a logical circuit, and at least one of the second semiconductor section or the third semiconductor section comprises a memory circuit.

15. The imaging device of claim 9, wherein the conductive material embedded in the fourth through hole portion contacts a pad of the third wiring layer of the third multilayer wiring layer.

16. The imaging device of claim 9, wherein the first connection portion is disposed such that light is blocked from one or more transistors residing in the second semiconductor section.

17. An electronic apparatus including:

an optical unit including at least one lens configured to receive incident light; and

an imaging device configured to receive the incident light, the imaging device including;

a first semiconductor section including a first multilayer wiring layer at one side thereof, the first semiconductor section further including a circuit region and a pixel region;

a second semiconductor section including a second multilayer wiring layer at one side thereof, the first and second semiconductor sections being secured together;

a third semiconductor section including a third multilayer wiring layer at one side thereof, the second and the third semiconductor sections being secured together such that the first semiconductor section, second semiconductor section, and the third semiconductor section are stacked together;

a first contact connecting a first wiring layer of the first multilayer wiring layer and, a conductive material disposed in a film of the second semiconductor section, the film of the second semiconductor section disposed at a side of the second semiconductor section that is opposite to the side at which the second multilayer wiring layer is disposed, wherein the first contact includes;

a first through hole portion penetrating a portion of the first semiconductor section in a vertical direction, wherein a conductive material embedded in the first through hole portion contacts the first wiring layer of the first multilayer wiring layer,

a second through hole portion penetrating a portion of the first semiconductor section and the first multilayer wiring layer in the vertical direction, wherein a conductive material embedded in the second through hole portion contacts the conductive material disposed in the film of the second semiconductor section, and

a first connection portion including a conductive material that connects the conductive material embedded in the first through hole portion and the conductive material embedded in the second through hole portion, wherein the first connection portion is above the first multilayer wiring layer in the vertical direction; and

a second contact connecting a second wiring layer of the second multilayer wiring layer and a third wiring layer of the third multilayer wiring layer, wherein the second contact includes;

a third through hole portion penetrating a portion of the second semiconductor section in the vertical direction, wherein a conductive material embedded in the third through hole portion contacts the second wiring layer of the second multilayer wiring layer, and

a fourth through hole portion penetrating a portion of the second semiconductor section, the second multilayer wiring layer, and a portion of the third multilayer wiring layer in the vertical direction, wherein a conductive material embedded in the fourth through hole portion contacts the third wiring layer of the third multilayer wiring layer, and wherein the conductive material disposed in the film of the second semiconductor section connects the conductive material embedded in the third through hole portion and the conductive material embedded in the fourth through hole portion.

18. The electronic apparatus of claim 17, wherein the first semiconductor section, the second semiconductor section, and the third semiconductor section are stacked together in a manner such that the second multilayer wiring layer faces the third multilayer wiring layer.

19. The electronic apparatus of claim 17, further comprising a pad electrode for external connection.

20. The electronic apparatus of claim 19, wherein the pad electrode is disposed such that light is blocked from one or more transistors residing in the second semiconductor section.

21. The electronic apparatus of claim 17, wherein the first semiconductor section comprises a sensor circuit, at least one of the second semiconductor section or the third semiconductor section comprises a logical circuit, and at least one of the second semiconductor section or the third semiconductor section comprises a memory circuit.

22. The electronic apparatus of claim 17, wherein the conductive material embedded in the fourth through hole portion contacts a pad of the third wiring layer of the third multilayer wiring layer.

23. The electronic apparatus of claim 17, wherein the first connection portion is disposed such that light is blocked from one or more transistors residing in the second semiconductor section.

24. The electronic apparatus of claim 17, wherein the film is an interlayer insulating film disposed between the first and second semiconductor sections.