System, method, and computer program product for improving memory systems

• US 9,432,298 B1
• Filed: 12/10/2012
• Issued: 08/30/2016
• Est. Priority Date: 12/09/2011
• Status: Active Grant

• Current Assignee: P4tents1 LLC
• Original Assignee: P4tents1 LLC
• Inventors: Smith, Michael S
• Primary Examiner(s): Thompson, Jr., Otis L
• Application Number:
  US13/710,411
• Time in Patent Office: 1,359 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/4824 Connecting between the body and an opposite side of the item with respect to the body
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H04L 47/34 ensuring sequence integrity, e.g. using sequence numbers
• CPC Class Codes: H04L 49/9057 Arrangements for supporting packet reassembly or resequencing

Abstract

A system, method, and computer program product are provided for a memory system. The system includes a first semiconductor platform including at least one first circuit, and at least one additional semiconductor platform stacked with the first semiconductor platform and including at least one additional circuit.

Claims

1. An apparatus, comprising:

a first semiconductor platform including a first memory;

a second semiconductor platform including a second memory; and

at least one circuit in electrical communication with at least one of the first semiconductor platform or the second semiconductor platform for transforming a plurality of commands or packets, or a portion thereof, in connection with at least one of the first memory or the second memory, by;

transforming a first memory command or packet, or a portion thereof, such that the first memory command or packet, or the portion thereof, is processed by the first memory of the first semiconductor platform and the first memory command or packet, or the portion thereof, avoids processing, at least in part, by the second memory of the second semiconductor platform; and

transforming a second memory command or packet, or a portion thereof, such that the second memory command or packet, or the portion thereof, avoids processing, at least in part, by the first memory of the first semiconductor platform and the second memory command or packet, or the portion thereof, is processed by the second memory of the second semiconductor platform.

2. The apparatus of claim 1, wherein the apparatus is operable such that the transforming includes re-ordering.

3. The apparatus of claim 1, wherein the apparatus is operable such that the transforming includes combining.

4. The apparatus of claim 1, wherein the apparatus is operable such that the transforming includes splitting.

5. The apparatus of claim 1, wherein the apparatus is operable such that the transforming includes modifying.

6. The apparatus of claim 1, wherein the second semiconductor platform is stacked with the first semiconductor platform.

7. A method, comprising:

transforming a first memory command or packet, or a portion thereof, such that the first memory command or packet, or the portion thereof, is processed by a first memory of a first semiconductor platform and the first memory command or packet, or the portion thereof, avoids processing, at least in part, by a second memory of a second semiconductor platform; and

transforming a second memory command or packet, or a portion thereof, such that the second memory command or packet, or the portion thereof, avoids processing, at least in part, by the first memory of the first semiconductor platform and the second memory command or packet, or the portion thereof, is processed by the second memory of the second semiconductor platform.

8. The method of claim 7, wherein the transforming includes re-ordering.

9. The method of claim 7, wherein the transforming includes combining.

10. The method of claim 7, wherein the transforming includes splitting.

11. The method of claim 7, wherein the transforming includes modifying.

12. The method of claim 7, wherein the second semiconductor platform is stacked with the first semiconductor platform.

13. A computer program product embodied on a non-transitory computer readable medium, comprising:

code for working with at least one circuit to transform a first memory command or packet, or a portion thereof, such that the first memory command or packet, or the portion thereof, is processed by a first memory of a first semiconductor platform and the first memory command or packet, or the portion thereof, avoids processing, at least in part, by a second memory of a second semiconductor platform; and

code for working with the at least one circuit to transform a second memory command or packet, or a portion thereof, such that the second memory command or packet, or the portion thereof, avoids processing, at least in part, by the first memory of the first semiconductor platform and the second memory command or packet, or the portion thereof, is processed by the second memory of the second semiconductor platform.

14. The computer program of claim 13, wherein the computer program product is operable such that the transforming includes re-ordering.

15. The computer program of claim 13, wherein the computer program product is operable such that the transforming includes combining.

16. The computer program of claim 13, wherein the computer program product is operable such that the transforming includes splitting.

17. The computer program of claim 13, wherein the computer program product is operable such that the transforming includes modifying.

18. The computer program of claim 13, wherein the second semiconductor platform is stacked with the first semiconductor platform.

19. An apparatus, comprising:

a first semiconductor platform including a first memory;

a second semiconductor platform including a second memory;

means for transforming a first memory command or packet, or a portion thereof, such that the first memory command or packet, or the portion thereof, is processed by the first memory of the first semiconductor platform and the first memory command or packet, or the portion thereof, avoids processing, at least in part, by the second memory of the second semiconductor platform; and

means for transforming a second memory command or packet, or a portion thereof, such that the second memory command or packet, or the portion thereof, avoids processing, at least in part, by the first memory of the first semiconductor platform and the second memory command or packet, or the portion thereof, is processed by the second memory of the second semiconductor platform.