Chip including memory element storing higher level memory data on a page by page basis

  • US 9,436,631 B2
  • Filed: 03/31/2014
  • Issued: 09/06/2016
  • Est. Priority Date: 03/05/2001
  • Status: Active Grant
First Claim
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1. A bus system for transferring data between parts of a multiprocessor system, the bus system comprising:

  • a plurality of bus segments for each processor of the multiprocessor system comprising a plurality of flexible data channels to each processor of the multiprocessor system according to algorithms to be executed, wherein a plurality of algorithms may executed in parallel;

    wherein a communication between a sender and a receiver is established in accordance with a data transfer for an executed algorithm; and

    at least one identifier is transmitted with the data for at least one of;

    identifying a source of the data transfer; and

    selecting a target of the data transfer.

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