Method of designing layout of integrated circuit and method of manufacturing integrated circuit

• US 9,436,792 B2
• Filed: 08/07/2015
• Issued: 09/06/2016
• Est. Priority Date: 08/22/2014
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Baek, Sang-hoon, Song, Tae-joong, Oh, Sang-kyu, Lee, Seung-young
• Primary Examiner(s): KIK, PHALLAKA
• Application Number:
  US14/820,983
• Publication Number:
  US 20160055286A1
• Time in Patent Office: 396 Days
• Field of Search: 716/54, 716/55, 716/53, 716/122, 716/129, 430/5, 378/35
• US Class Current: 1/1
• CPC Class Codes: G03F 1/00 Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
• CPC Class Codes: G06F 2119/18 Manufacturability analysis or optimisation for manufacturability
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: G16Z 99/00 Subject matter not provided for in other main groups of this subclass
• CPC Class Codes: G21K 5/00 Irradiation devices discharge tubes for irradiating H01J37/00

Abstract

A method of designing a layout of an integrated chip (IC) includes designing a first layout by place and route a plurality of standard cells that define the IC, and generating a second layout by modifying the first layout during a mask data preparation process related to the first layout, wherein the second layout is generated by connecting first and second patterns from among first layer patterns that correspond to a first layer of the first layout, such that the number of masks necessary for forming the first layer patterns is reduced.

Claims

1. A computer-implemented method of fabricating an integrated chip (IC), the method comprising:

designing a first layout by placing and routing a plurality of standard cells that define the IC;

generating a second layout by modifying the first layout during a mask data preparation process related to the first layout, wherein the second layout is generated by connecting first and second patterns from among first layer patterns corresponding to a first layer of the first layout, such that a single mask is applied to the connected first and second patterns, thereby reducing the number of masks necessary for forming the first layer patterns of the first layer of the IC; and

manufacturing the IC according to the second layout.

2. The method of claim 1, wherein the first and second patterns are positioned in parallel to each other in a first direction and extend in a second direction that is substantially perpendicular to the first direction.

3. The method of claim 2, wherein the generating of the second layout comprises generating the second layout comprising a new pattern that is generated by merging the first and second patterns, has a first width that is greater than respective widths of the first and second patterns in the first direction, and is formed using a single mask.

4. The method of claim 2, wherein the generating of the second layout comprises generating the second layout comprising a new pattern that includes the first and second patterns and a bridge pattern connecting the first and second patterns together using a cross-connecting pattern, and is formed using a single mask.

5. The method of claim 2, wherein the generating of the second layout comprises generating the second layout comprising new first and second patterns that have a smaller height in the second direction than the first and second patterns and are formed using a single mask, and a second layer that is commonly connected to the new first and second patterns.

6. The method of claim 5, wherein the first layout further comprises a plurality of conductive lines that are positioned in parallel to the first and second patterns, and

wherein the second layer is a contact that is to be formed on at least one selected from the plurality of conductive lines and on the new first and second patterns.

7. The method of claim 2, wherein the generating of the second layout comprises generating the second layout that comprises:

a new first pattern that has a smaller height than the first and second patterns in the second direction such that a distance between the new first pattern and a third pattern from among the first layer patterns is the same or greater than a threshold distance, wherein the new first pattern and the third pattern are formed using the same mask; and

a second layer having a form of a bridge that connects the new first pattern and the second pattern.

8. The method of claim 7, wherein the first layout further comprises a plurality of conductive lines that are positioned in parallel to the first and second patterns, and

the second layer is a contact that is to be formed on the new first pattern, the second pattern, and at least one selected from the plurality of conductive lines.

9. The method of claim 1, wherein the first layer comprises a contact that is electrically connected to an active area of the IC and is to be formed on the active area.

10. The method of claim 9, wherein the first and second patterns respectively correspond to first and second power contact patterns.

11. The method of claim 10, wherein the first and second power contact patterns are included in a first standard cell, and patterns other than the first and second power contact patterns from among the first layer patterns are included in a second standard cell that is adjacent to the first standard cell in a second direction in which the first and second patterns extend.

12. The method of claim 10, wherein the first power contact pattern is included in a first standard cell, the second power contact pattern is included in a second standard cell that is adjacent to the first standard cell in a first direction, and patterns other than the first and second power contact patterns from among the first layer patterns are included in a third standard cell that is adjacent to one of the first and second standard cells in a second direction in which the first and second patterns extend.

13. A method of designing a layout of a standard cell of an integrated circuit (IC), the method comprising;

configuring a first layout by placing and routing a standard cell, the standard cell including first and second patterns from among first layer patterns corresponding to a first layer of the first layout;

configuring a second layout by modifying the first layout by connecting the first and second patterns among the first layer patterns so that the number of masks required to form the first layer patterns of the standard cell according to the second layout is reduced relative to the number of masks required to form the first layer patterns of the standard cell according to the first layout; and

manufacturing the integrated circuit based on the second layout.

14. The method of claim 13, wherein the first and second patterns are positioned in parallel to each other in a first direction and extend in a second direction that is substantially perpendicular to the first direction, and wherein the configuring of the second layout comprises at least one of:

configuring the second layout comprising a new pattern that is generated by merging the first and second patterns, has a first width that is greater than respective widths of the first and second patterns in the first direction, and is formed using a single mask;

configuring the second layout comprising a new pattern that includes the first and second patterns and a bridge pattern connecting the first and second patterns together using a cross-connecting pattern, and is formed using a single mask;

or

configuring the second layout comprising new first and second patterns that have a smaller height in the second direction than the first and second patterns and are formed using a single mask, and a second layer that is commonly connected to the new first and second patterns.

15. The method of claim 13, wherein the first and second patterns are positioned in parallel to each other in a first direction and extend in a second direction that is substantially perpendicular to the first direction, and wherein the configuring of the second layout comprises generating the second layout that comprises:

a new first pattern that has a smaller height than the first and second patterns in the second direction such that a distance between the new first pattern and a third pattern from among the first layer patterns is the same or greater than a threshold distance, wherein the new first pattern and the third pattern are formed using the same mask; and

a second layer having a form of a bridge that connects the new first pattern and the second pattern.

16. The method of claim 15, wherein the first layout further comprises a plurality of conductive lines that are positioned in parallel to the first and second patterns, and

the second layer is a contact that is to be formed on the new first pattern, the second pattern, and at least one selected from the plurality of conductive lines.

17. The method of claim 16, wherein the first layer comprises a contact that is electrically connected to an active area of the IC and is to be formed on the active area and wherein the first and second patterns respectively correspond to first and second power contact patterns.