NAND flash memory having an enhanced buffer read capability and method of operation thereof

• US 9,442,798 B2
• Filed: 07/31/2014
• Issued: 09/13/2016
• Est. Priority Date: 07/31/2014
• Status: Active Grant

• Current Assignee: Winbond Electronics Corporation
• Original Assignee: Winbond Electronics Corporation
• Inventors: Michael, Oron, Gupta, Anil
• Primary Examiner(s): ABRAHAM, ESAW T
• Application Number:
  US14/448,945
• Publication Number:
  US 20160034352A1
• Time in Patent Office: 775 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 11/1064 in cache or content addressable memories
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 2029/0411 Online error correction

Abstract

A page buffer suitable for continuous page read may be implemented with a partitioned data register, a partitioned cache register, and a suitable ECC circuit. The partitioned data register, partitioned cache register, and associated ECC circuit may also be used to realize a substantial improvement in the page read operation by using a modified Page Data Read instruction and/or a Buffer Read instruction, including in some implementations the use of a partition busy bit.

Claims

1. A method of operating a digital memory device to read data from a page of data stored therein to a data bus, comprising:

receiving a page data read instruction specifying a page of the digital memory device;

responsive to the page data read instruction receiving step, setting a first status bit and a second status bit to “

busy;

”

responsive to the page data read instruction receiving step, loading data from the specified page of data into a page buffer in the digital memory device, the page buffer being partitioned into at least a first part and a second part;

responsive to the page data read instruction receiving step, performing first ECC processing of the data in the first part of the page buffer to establish first ECC-processed data therein;

resetting the first status bit to “

not busy”

upon completion of the first ECC processing performing step;

responsive to the page data read instruction receiving step, performing second ECC processing of the data in a second part of the page buffer to establish second ECC-processed data therein; and

resetting the second status bit to “

not busy”

upon completion of the second ECC processing performing step.

2. The method of claim 1, further comprising:

receiving a buffer read instruction; and

responsive to the buffer read instruction receiving step, outputting the first ECC-processed data from the first part of the page buffer to the data bus, in an overlapping relationship with the second ECC processing performing step.

3. The method of claim 2, further comprising:

responsive to the buffer read instruction receiving step, determining in an internal operation of the digital memory device that the second status bit indicates “

not busy;

” and

responsive to the buffer read instruction receiving step and the determining step, outputting the second ECC-processed data from the second part of the page buffer to the data bus contiguously with the first ECC-processed data outputting step.

4. The method of claim 2, further comprising:

responsive to the buffer read instruction receiving step, determining in an internal operation of the digital memory device that the second status bit indicates “

busy;

” and

responsive to the buffer read instruction receiving step and the determining step, terminating output from the page buffer upon completion of the first ECC-processed data outputting step.

5. The method of claim 1, further comprising:

receiving a read status register instruction;

responsive to the read status register instruction receiving step, determining that the second status bit indicates “

not busy;

” and

responsive to the buffer read instruction receiving step and the determining step, outputting the second ECC-processed data from the second part of the page buffer to the data bus.

6. The method of claim 1, wherein:

the page buffer comprises a cache register and a data register, the first part of the page buffer comprising a first part of the cache register and a first part of the data register, and the second part of the page buffer comprising a second part of the cache register and a second part of the data register;

the data loading step comprises loading data from the specified page of data into the data register, and replicating the data into the cache register;

the first ECC processing performing step comprises performing the first ECC processing of the data in the first part of the cache register to establish the first ECC-processed data therein; and

the second ECC processing performing step comprises performing the second ECC processing of the data in the second part of the cache register to establish the second ECC-processed data therein.

7. A method of operating a digital memory device to read data from a page of data stored therein, comprising:

receiving a page data read instruction specifying a page of the digital memory device;

responsive to the page data read instruction receiving step, loading data from the specified page of data into a page buffer in the digital memory device, the page buffer being partitioned into at least a first part and a second part;

responsive to the page data read instruction receiving step, performing first ECC processing of the data in the first part of the page buffer to establish first ECC-processed data therein;

receiving a buffer read instruction;

responsive to the buffer read instruction receiving step, outputting the first ECC-processed data from the first part of the page buffer to a data bus; and

performing, in an overlapping relationship with the first ECC-processed data outputting step, second ECC processing of the data in a second part of the page buffer to establish second ECC-processed data therein.

8. The method of claim 7 further comprising:

responsive to the page data read instruction receiving step, setting a partition busy bit to “

busy;

” and

resetting the partition busy bit to “

not busy”

upon completion of the second ECC processing performing step.

9. The method of claim 8 further comprising:

detecting the “

not busy”

status of the partition busy bit from the resetting step; and

responsive to the detecting step, outputting the second ECC-processed data in the second part of the page buffer to the data bus resetting step.

10. The method of claim 8 further comprising:

detecting the “

not busy”

status of the partition busy bit from the resetting step;

receiving a further buffer read instruction; and

responsive to the further buffer read instruction receiving step and to the detecting step, outputting the second ECC-processed data in the second part of the page buffer.

11. The method of claim 7 wherein the second ECC processing performing step is responsive to the page data read instruction receiving step.

12. The method of claim 7 wherein the second ECC processing performing step is responsive to the buffer read instruction receiving step.

13. The method of claim 7:

wherein the page buffer comprises a data register partitioned into a plurality of parts, and a cache register partitioned into a plurality of parts corresponding to the parts of the data register; and

wherein the loading step comprises loading data from the specified page of data into the data register;

further comprising replicating the data in the data register to the cache register;

wherein the first ECC processing performing step comprises performing ECC processing of the data in the first part of the cache register to establish the first ECC-processed data therein;

wherein the first ECC-processed data outputting step comprises outputting the first ECC-processed data from the first part of the cache register to the data bus;

wherein the second ECC processing performing step comprises performing ECC processing of the data in the second part of the cache register to establish the second ECC-processed data therein; and

wherein the second ECC-processed data outputting step comprises outputting the second ECC-processed data from the second part of the cache register to the data bus.

14. The method of claim 7 further comprising:

responsive to the page data read instruction receiving step, setting a status bit to “

busy;

” and

resetting the status bit to “

not busy”

upon completion of the first ECC processing performing step.

15. A digital memory device comprising:

a NAND flash memory array;

a row decoder coupled to the NAND flash memory array;

a data register coupled to the NAND flash memory array;

a cache register coupled to the data register;

an ECC circuit coupled to the cache register;

a column decoder coupled to the cache register; and

a control circuit coupled to the row decoder, the column decoder, the data register, the cache register, and the ECC circuit, wherein the control circuit comprises logic and register elements for executing the functions of;

receiving a page data read instruction specifying a page of the digital memory device;

responsive to the page data read instruction receiving function, loading data from the specified page of data into a page buffer in the digital memory device, the page buffer being partitioned into at least a first part and a second part;

responsive to the page data read instruction receiving function, performing first ECC processing of the data in the first part of the page buffer to establish first ECC-processed data therein;

receiving a buffer read instruction;

responsive to the buffer read instruction receiving function, outputting the first ECC-processed data from the first part of the page buffer to a data bus; and

performing, in an overlapping relationship with the first ECC-processed data outputting step, second ECC processing of the data in a second part of the page buffer to establish second ECC-processed data therein.

16. The digital memory device of claim 15 further comprising a partition busy bit, wherein the control circuit further comprises logic and register elements for executing the functions of:

responsive to the page data read instruction receiving function, setting a partition busy bit to “

busy;

” and

resetting the partition busy bit to “

not busy”

upon completion of the second ECC processing performing function.

17. The digital memory device of claim 15 further comprising a partition busy bit, wherein the control circuit further comprises logic and register elements for executing the functions of:

responsive to the buffer read instruction receiving function, setting a partition busy bit to “

busy;

” and

resetting the partition busy bit to “

not busy”

upon completion of the second ECC processing performing function.

18. The digital memory device of claim 15, wherein second ECC processing performing function is responsive to the page data read instruction receiving function.

19. The digital memory device of claim 15, wherein second ECC processing performing function is responsive to the buffer read instruction receiving function.

20. The digital memory device of claim 15 further comprising a status bit, wherein the control circuit further comprises logic and register elements for executing the functions of:

responsive to the page data read instruction receiving step, setting the status bit to “

busy;

” and

resetting the status bit to “

not busy”

upon completion of the first ECC processing performing step.