Semiconductor device and method of manufacturing the same

• US 9,443,870 B2
• Filed: 09/15/2015
• Issued: 09/13/2016
• Est. Priority Date: 09/05/2013
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Shinohara, Hirofumi, Oda, Hidekazu, Iwamatsu, Toshiaki
• Primary Examiner(s): KIELIN, ERIK J
• Application Number:
  US14/855,150
• Publication Number:
  US 20160005765A1
• Time in Patent Office: 364 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/76229 Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
• CPC Class Codes: H01L 21/76264 SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/36 characterised by the concentration or distribution of impurities in the bulk material within semiconductor regions H01L29/06
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/66598 forming drain [D] and lightly doped drain [LDD] simultaneously, e.g. using implantation through the wings a T-shaped layer, or through a specially shaped layer
• CPC Class Codes: H01L 29/66681 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7824 with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

In an SOI substrate having a semiconductor layer formed on the semiconductor substrate via an insulating layer, a MISFET is formed in each of the semiconductor layer in an nMIS formation region and a pMIS formation region. In power feeding regions, the semiconductor layer and the insulating layer are removed. In the semiconductor substrate, a p-type semiconductor region is formed so as to include the nMIS formation region and one of the power feeding regions, and an n-type semiconductor region is formed so as to include a pMIS formation region and the other one of the power feeding regions. In the semiconductor substrate, a p-type well having lower impurity concentration than the p-type semiconductor region is formed so as to contain the p-type semiconductor region, and an n-type well having lower impurity concentration than the n-type semiconductor region is formed so as to contain the n-type semiconductor region.

Claims

1. A semiconductor device comprising:

a semiconductor substrate including a first region and a second region;

an insulating layer formed over the first region of the semiconductor substrate;

a semiconductor layer formed over the insulating layer;

a device isolation region penetrating through the semiconductor layer, the insulating layer and the semiconductor substrate; and

a MISFET formed over the first region,

wherein a first semiconductor region of a first conductivity type is formed in the first region and the second region,

wherein a second semiconductor region of the first conductivity type is formed in the first semiconductor region of the first region and the second region and is formed in order to be surrounded by the first semiconductor region in a plan view,

wherein a third semiconductor region of the first conductivity type is formed in the second semiconductor region of the first region,

wherein the semiconductor layer and the insulating layer are removed in the second region,

wherein the second semiconductor region extends under the device isolation region interposed between the first region and the second region,

wherein an impurity concentration of the second semiconductor region is higher than that of the first semiconductor region, and

wherein an impurity concentration of the third semiconductor region is higher than that of the second semiconductor region.

2. The semiconductor device according to claim 1,

wherein a plug is disposed over the second semiconductor region of the second region, and

wherein a voltage for controlling a threshold voltage of the MISFET is supplied from the plug via the second semiconductor region to the third semiconductor region.

3. The semiconductor device according to claim 2,

wherein a fourth semiconductor region of the first conductivity type is formed in the second semiconductor region of the second region and is electrically connect with the plug, and

wherein a bottom of the fourth semiconductor region is shallower than that of the device isolation region.

4. The semiconductor device according to claim 3, further comprising:

a metal silicide layer formed on the fourth semiconductor region.

5. The semiconductor device according to claim 1,

wherein a depth of the device isolation is set on the order to 250 nm to 350 nm.

6. The semiconductor device according to claim 1,

wherein the MISFET has a first gate electrode formed over the semiconductor layer via a first gate insulating film.

7. The semiconductor device according to claim 1,

wherein the MISFET is a n-channel-type MISFET, and

wherein the first conductivity type is p-type.

8. The semiconductor device according to claim 1,

wherein the MISFET is a p-channel-type MISFET, and

wherein the first conductivity type is n-type.