Semiconductor chip including region having integrated circuit transistor gate electrodes formed by various conductive structures of specified shape and position and method for manufacturing the same

• US 9,443,947 B2
• Filed: 05/13/2015
• Issued: 09/13/2016
• Est. Priority Date: 03/09/2006
• Status: Active Grant

• Current Assignee: RPX Corporation
• Original Assignee: Tela Innovations, Inc.
• Inventors: Becker, Scott T., Smayling, Michael C.
• Primary Examiner(s): HOANG, QUOC DINH
• Application Number:
  US14/711,731
• Publication Number:
  US 20150249041A1
• Time in Patent Office: 489 Days
• Field of Search: 257/202, 257/204, 257/206, 257/211, 257/365
• US Class Current: 1/1
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: H01L 2027/11812 4-T CMOS basic cell
• CPC Class Codes: H01L 2027/11814 5-T CMOS basic cell
• CPC Class Codes: H01L 2027/11855 Twin-tub technology
• CPC Class Codes: H01L 2027/11861 Substrate and well contacts
• CPC Class Codes: H01L 2027/11862 Horizontal or vertical grid line density
• CPC Class Codes: H01L 2027/11864 Yield or reliability
• CPC Class Codes: H01L 2027/11866 Gate electrode terminals or contacts
• CPC Class Codes: H01L 2027/11875 Wiring region, routing
• CPC Class Codes: H01L 2027/11887 Three levels of metal
• CPC Class Codes: H01L 2027/11888 More than 3 levels of metal
• CPC Class Codes: H01L 21/28123 Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
• CPC Class Codes: H01L 21/823871 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/11807 CMOS gate arrays
• CPC Class Codes: H01L 29/42372 : characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/42376 : characterised by the length or the sectional shape
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor chip includes a region that includes a first conductive structure (CS) that forms a gate electrode (GE) of a first transistor of a first transistor type. The region includes a second CS that forms a GE of a second transistor of the first transistor type and a GE of a first transistor of a second transistor type. The region includes another CS that forms a GE of a second transistor of the second transistor type. The GE'"'"'s of the first and second transistors of the first transistor type are separated by a gate pitch. The GE'"'"'s of the first and second transistors of the second transistor type are separated by the gate pitch. The first CS has a total length that is greater than one-half of the total length of the second CS. The second and third CS'"'"'s have at least one respective end aligned with each other.

Claims

1. A semiconductor chip, comprising:

a region including a plurality of transistors, each of the plurality of transistors in the region forming part of circuitry associated with execution of one or more logic functions, the region including at least eight conductive structures formed within the semiconductor chip, some of the at least eight conductive structures forming at least one transistor gate electrode,

each of the at least eight conductive structures respectively having a corresponding top surface, wherein an entirety of a periphery of the corresponding top surface is defined by a corresponding first end, a corresponding second end, a corresponding first edge, and a corresponding second edge, such that a total distance along the entirety of the periphery of the corresponding top surface is equal to a sum of a total distance along the corresponding first edge and a total distance along the corresponding second edge and a total distance along the corresponding first end and a total distance along the corresponding second end,

wherein the total distance along the corresponding first edge is greater than two times the total distance along the corresponding first end,

wherein the total distance along the corresponding first edge is greater than two times the total distance along the corresponding second end,

wherein the total distance along the corresponding second edge is greater than two times the total distance along the corresponding first end,

wherein the total distance along the corresponding second edge is greater than two times the total distance along the corresponding second end,

wherein the corresponding first end extends from the corresponding first edge to the corresponding second edge and is located principally within a space between the corresponding first and second edges,

wherein the corresponding second end extends from the corresponding first edge to the corresponding second edge and is located principally within the space between the corresponding first and second edges,

the top surfaces of the at least eight conductive structures co-planar with each other,

each of the at least eight conductive structures having a corresponding lengthwise centerline oriented in a first direction along its top surface and extending from its first end to its second end,

each of the at least eight conductive structures having a length as measured along its lengthwise centerline from its first end to its second end,

wherein the first edge of each of the at least eight conductive structures is substantially straight,

wherein the second edge of each of the at least eight conductive structures is substantially straight,

each of the at least eight conductive structures having both its first edge and its second edge oriented substantially parallel to its lengthwise centerline,

each of the at least eight conductive structures having a width measured in a second direction perpendicular to the first direction at a midpoint of its lengthwise centerline,

each of the first direction and the second direction oriented substantially parallel to the co-planar top surfaces of the at least eight conductive structures,

wherein the at least eight conductive structures are positioned in a side-by-side manner such that each of the at least eight conductive structures is positioned to have at least a portion of its length beside at least a portion of the length of another of the at least eight conductive structures,

wherein the width of each of the at least eight conductive structures is less than 45 nanometers, the region having a size of about 965 nanometers as measured in the second direction, each of the at least eight conductive structures positioned such that a distance as measured in the second direction between its lengthwise centerline and the lengthwise centerline of at least one other of the at least eight conductive structures is substantially equal to a first pitch that is less than or equal to about 193 nanometers,

the region including a first transistor of a first transistor type, a second transistor of the first transistor type, a first transistor of a second transistor type, and a second transistor of the second transistor type,

wherein each transistor of the first transistor type having its gate electrode formed by any of the at least eight conductive structures is included in a first collection of transistors, and wherein each transistor of the second transistor type having its gate electrode formed by any of the at least eight conductive structures is included in a second collection of transistors, wherein the first and second collections of transistors are separated from each other by an inner sub-region of the region, wherein the inner sub-region does not include a source or a drain of any transistor,

the first transistor of the first transistor type having a gate electrode formed by a portion of a first conductive structure of the at least eight conductive structures, wherein any transistor having its gate electrode formed by the first conductive structure is of the first transistor type,

the second transistor of the first transistor type having a gate electrode formed by a portion of a second conductive structure of the at least eight conductive structures, the first transistor of the second transistor type having a gate electrode formed by another portion of the second conductive structure, the second conductive structure positioned such that its lengthwise centerline is separated from the lengthwise centerline of the first conductive structure by the first pitch as measured in the second direction,

the second transistor of the second transistor type having a gate electrode formed by one of the at least eight conductive structures, the conductive structure that forms the gate electrode of the second transistor of the second transistor type positioned such that its lengthwise centerline is separated from the lengthwise centerline of the second conductive structure by the first pitch as measured in the second direction, wherein any transistor having its gate electrode formed by the conductive structure that forms the gate electrode of the second transistor of the second transistor type is of the second transistor type,

the first conductive structure having a total length as measured in the first direction that is greater than one-half of a total length of the second conductive structure as measured in the first direction,

the second conductive structure having at least one end substantially positioned at a first reference line oriented in the second direction, and the conductive structure that forms the gate electrode of the second transistor of the second transistor type also having at least one end substantially positioned at the first reference line.

2. The semiconductor chip as recited in claim 1, wherein the region includes a first interconnect conductive structure positioned within either of a first interconnect level, a second interconnect level, a third interconnect level, or a fourth interconnect level,

the first interconnect conductive structure having a top surface, an entirety of a periphery of the top surface of the first interconnect conductive structure defined by a first end of the first interconnect conductive structure, a second end of the first interconnect conductive structure, a first edge of the first interconnect conductive structure, and a second edge of the first interconnect conductive structure, such that a total distance along the entirety of the periphery of the top surface of the first interconnect conductive structure is equal to a sum of a total distance along the first edge of the first interconnect conductive structure and a total distance along the second edge of the first interconnect conductive structure and a total distance along the first end of the first interconnect conductive structure and a total distance along the second end of the first interconnect conductive structure,

wherein the total distance along the first edge of the first interconnect conductive structure is greater than two times the total distance along the first end of the first interconnect conductive structure,

wherein the total distance along the first edge of the first interconnect conductive structure is greater than two times the total distance along the second end of the first interconnect conductive structure,

wherein the total distance along the second edge of the first interconnect conductive structure is greater than two times the total distance along the first end of the first interconnect conductive structure,

wherein the total distance along the second edge of the first interconnect conductive structure is greater than two times the total distance along the second end of the first interconnect conductive structure,

wherein the first end of the first interconnect conductive structure extends from the first edge of the first interconnect conductive structure to the second edge of the first interconnect conductive structure and is located principally within a space between the first and second edges of the first interconnect conductive structure,

wherein the second end of the first interconnect conductive structure extends from the first edge of the first interconnect conductive structure to the second edge of the first interconnect conductive structure and is located principally within the space between the first and second edges of the first interconnect conductive structure,

the first interconnect conductive structure having a lengthwise centerline oriented in the first direction along its top surface and extending from its first end to its second end,

wherein the first edge of the first interconnect conductive structure is substantially straight and is oriented substantially parallel to the lengthwise centerline of the first interconnect conductive structure,

wherein the second edge of the first interconnect conductive structure is substantially straight and is oriented substantially parallel to the lengthwise centerline of the first interconnect conductive structure,

wherein the first interconnect conductive structure has a length measured along its lengthwise centerline from its first end to its second end,

wherein the first interconnect conductive structure has a width measured in the second direction perpendicular to the first direction at a midpoint of the lengthwise centerline of the first interconnect conductive structure,

wherein the first interconnect level is formed at a vertical position within the semiconductor chip above the at least eight conductive structures, wherein the first interconnect level is separated from the co-planar top surfaces of the at least eight conductive structures by at least one dielectric material,

wherein the second interconnect level is formed at a vertical position within the semiconductor chip above the first interconnect level,

wherein the third interconnect level is formed at a vertical position within the semiconductor chip above the second interconnect level, and

wherein the fourth interconnect level is formed at a vertical position within the semiconductor chip above the third interconnect level.

3. The semiconductor chip as recited in claim 2, wherein the region includes a second interconnect conductive structure positioned next to and spaced apart from the first interconnect conductive structure in a same interconnect level as the first interconnect conductive structure,

the second interconnect conductive structure having a top surface, an entirety of a periphery of the top surface of the second interconnect conductive structure defined by a first end of the second interconnect conductive structure, a second end of the second interconnect conductive structure, a first edge of the second interconnect conductive structure, and a second edge of the second interconnect conductive structure, such that a total distance along the entirety of the periphery of the top surface of the second interconnect conductive structure is equal to a sum of a total distance along the first edge of the second interconnect conductive structure and a total distance along the second edge of the second interconnect conductive structure and a total distance along the first end of the second interconnect conductive structure and a total distance along the second end of the second interconnect conductive structure,

wherein the total distance along the first edge of the second interconnect conductive structure is greater than two times the total distance along the first end of the second interconnect conductive structure,

wherein the total distance along the first edge of the second interconnect conductive structure is greater than two times the total distance along the second end of the second interconnect conductive structure,

wherein the total distance along the second edge of the second interconnect conductive structure is greater than two times the total distance along the first end of the second interconnect conductive structure,

wherein the total distance along the second edge of the second interconnect conductive structure is greater than two times the total distance along the second end of the second interconnect conductive structure,

wherein the first end of the second interconnect conductive structure extends from the first edge of the second interconnect conductive structure to the second edge of the second interconnect conductive structure and is located principally within a space between the first and second edges of the second interconnect conductive structure,

wherein the second end of the second interconnect conductive structure extends from the first edge of the second interconnect conductive structure to the second edge of the second interconnect conductive structure and is located principally within the space between the first and second edges of the second interconnect conductive structure,

the second interconnect conductive structure having a lengthwise centerline oriented in the first direction along its top surface and extending from its first end to its second end,

wherein the first edge of the second interconnect conductive structure is substantially straight and is oriented substantially parallel to the lengthwise centerline of the second interconnect conductive structure,

wherein the second edge of the second interconnect conductive structure is substantially straight and is oriented substantially parallel to the lengthwise centerline of the second interconnect conductive structure,

wherein the second interconnect conductive structure has a length measured along its lengthwise centerline from its first end to its second end,

wherein the second interconnect conductive structure has a width measured in the second direction perpendicular to the first direction at a midpoint of the lengthwise centerline of the second interconnect conductive structure.

4. The semiconductor chip as recited in claim 3, wherein the first and second interconnect conductive structures are positioned such that a distance as measured in the second direction between their lengthwise centerlines is substantially equal to a second pitch, wherein the second pitch is a fractional multiple of the first pitch.

5. The semiconductor chip as recited in claim 4, wherein the second pitch is less than or equal to the first pitch.

6. The semiconductor chip as recited in claim 5, wherein at least one of the at least eight conductive structures within the region does not form a gate electrode of any transistor and has a width as measured in the second direction that is substantially equal to a width as measured in the second direction of another of the at least eight conductive structures.

7. The semiconductor chip as recited in claim 6, wherein the first and second interconnect conductive structures are positioned within either of the first interconnect level, the second interconnect level, or the third interconnect level.

8. The semiconductor chip as recited in claim 1, wherein the region includes a first interconnect conductive structure positioned within either of a first interconnect level, a second interconnect level, a third interconnect level, or a fourth interconnect level,

the first interconnect conductive structure having a top surface, an entirety of a periphery of the top surface of the first interconnect conductive structure defined by a first end of the first interconnect conductive structure, a second end of the first interconnect conductive structure, a first edge of the first interconnect conductive structure, and a second edge of the first interconnect conductive structure, such that a total distance along the entirety of the periphery of the top surface of the first interconnect conductive structure is equal to a sum of a total distance along the first edge of the first interconnect conductive structure and a total distance along the second edge of the first interconnect conductive structure and a total distance along the first end of the first interconnect conductive structure and a total distance along the second end of the first interconnect conductive structure,

wherein the total distance along the first edge of the first interconnect conductive structure is greater than two times the total distance along the first end of the first interconnect conductive structure,

wherein the total distance along the first edge of the first interconnect conductive structure is greater than two times the total distance along the second end of the first interconnect conductive structure,

wherein the total distance along the second edge of the first interconnect conductive structure is greater than two times the total distance along the first end of the first interconnect conductive structure,

wherein the total distance along the second edge of the first interconnect conductive structure is greater than two times the total distance along the second end of the first interconnect conductive structure,

wherein the first end of the first interconnect conductive structure extends from the first edge of the first interconnect conductive structure to the second edge of the first interconnect conductive structure and is located principally within a space between the first and second edges of the first interconnect conductive structure,

wherein the second end of the first interconnect conductive structure extends from the first edge of the first interconnect conductive structure to the second edge of the first interconnect conductive structure and is located principally within the space between the first and second edges of the first interconnect conductive structure,

the first interconnect conductive structure having a lengthwise centerline oriented in the second direction along its top surface and extending from its first end to its second end,

wherein the first edge of the first interconnect conductive structure is substantially straight and is oriented substantially parallel to the lengthwise centerline of the first interconnect conductive structure,

wherein the second edge of the first interconnect conductive structure is substantially straight and is oriented substantially parallel to the lengthwise centerline of the first interconnect conductive structure,

wherein the first interconnect conductive structure has a length measured along its lengthwise centerline from its first end to its second end,

wherein the first interconnect conductive structure has a width measured in the first direction perpendicular to the second direction at a midpoint of the lengthwise centerline of the first interconnect conductive structure,

wherein the first interconnect level is formed at a vertical position within the semiconductor chip above the at least eight conductive structures, wherein the first interconnect level is separated from the co-planar top surfaces of the at least eight conductive structures by at least one dielectric material,

wherein the second interconnect level is formed at a vertical position within the semiconductor chip above the first interconnect level,

wherein the third interconnect level is formed at a vertical position within the semiconductor chip above the second interconnect level, and

wherein the fourth interconnect level is formed at a vertical position within the semiconductor chip above the third interconnect level.

9. The semiconductor chip as recited in claim 8, wherein the region includes a second interconnect conductive structure positioned in a same interconnect level as the first interconnect conductive structure,

the second interconnect conductive structure having a top surface, an entirety of a periphery of the top surface of the second interconnect conductive structure defined by a first end of the second interconnect conductive structure, a second end of the second interconnect conductive structure, a first edge of the second interconnect conductive structure, and a second edge of the second interconnect conductive structure, such that a total distance along the entirety of the periphery of the top surface of the second interconnect conductive structure is equal to a sum of a total distance along the first edge of the second interconnect conductive structure and a total distance along the second edge of the second interconnect conductive structure and a total distance along the first end of the second interconnect conductive structure and a total distance along the second end of the second interconnect conductive structure,

wherein the total distance along the first edge of the second interconnect conductive structure is greater than two times the total distance along the first end of the second interconnect conductive structure,

wherein the total distance along the first edge of the second interconnect conductive structure is greater than two times the total distance along the second end of the second interconnect conductive structure,

wherein the total distance along the second edge of the second interconnect conductive structure is greater than two times the total distance along the first end of the second interconnect conductive structure,

wherein the total distance along the second edge of the second interconnect conductive structure is greater than two times the total distance along the second end of the second interconnect conductive structure,

wherein the first end of the second interconnect conductive structure extends from the first edge of the second interconnect conductive structure to the second edge of the second interconnect conductive structure and is located principally within a space between the first and second edges of the second interconnect conductive structure,

wherein the second end of the second interconnect conductive structure extends from the first edge of the second interconnect conductive structure to the second edge of the second interconnect conductive structure and is located principally within the space between the first and second edges of the second interconnect conductive structure,

the second interconnect conductive structure having a lengthwise centerline oriented in the second direction along its top surface and extending from its first end to its second end,

wherein the first edge of the second interconnect conductive structure is substantially straight and is oriented substantially parallel to the lengthwise centerline of the second interconnect conductive structure,

wherein the second edge of the second interconnect conductive structure is substantially straight and is oriented substantially parallel to the lengthwise centerline of the second interconnect conductive structure,

wherein the second interconnect conductive structure has a length measured along its lengthwise centerline from its first end to its second end,

wherein the second interconnect conductive structure has a width measured in the first direction perpendicular to the second direction at a midpoint of the lengthwise centerline of the second interconnect conductive structure,

wherein the first and second interconnect conductive structures are positioned next to and spaced apart from each other such that a distance as measured in the first direction between their lengthwise centerlines is substantially equal to a second pitch.

10. The semiconductor chip as recited in claim 9, wherein the region includes a third interconnect conductive structure positioned in the same interconnect level as the first and second interconnect conductive structures,

the third interconnect conductive structure having a top surface, an entirety of a periphery of the top surface of the third interconnect conductive structure defined by a first end of the third interconnect conductive structure, a second end of the third interconnect conductive structure, a first edge of the third interconnect conductive structure, and a second edge of the third interconnect conductive structure, such that a total distance along the entirety of the periphery of the top surface of the third interconnect conductive structure is equal to a sum of a total distance along the first edge of the third interconnect conductive structure and a total distance along the second edge of the third interconnect conductive structure and a total distance along the first end of the third interconnect conductive structure and a total distance along the second end of the third interconnect conductive structure,

wherein the total distance along the first edge of the third interconnect conductive structure is greater than two times the total distance along the first end of the third interconnect conductive structure,

wherein the total distance along the first edge of the third interconnect conductive structure is greater than two times the total distance along the second end of the third interconnect conductive structure,

wherein the total distance along the second edge of the third interconnect conductive structure is greater than two times the total distance along the first end of the third interconnect conductive structure,

wherein the total distance along the second edge of the third interconnect conductive structure is greater than two times the total distance along the second end of the third interconnect conductive structure,

wherein the first end of the third interconnect conductive structure extends from the first edge of the third interconnect conductive structure to the second edge of the third interconnect conductive structure and is located principally within a space between the first and second edges of the third interconnect conductive structure,

wherein the second end of the third interconnect conductive structure extends from the first edge of the third interconnect conductive structure to the second edge of the third interconnect conductive structure and is located principally within the space between the first and second edges of the third interconnect conductive structure,

the third interconnect conductive structure having a lengthwise centerline oriented in the second direction along its top surface and extending from its first end to its second end,

wherein the first edge of the third interconnect conductive structure is substantially straight and is oriented substantially parallel to the lengthwise centerline of the third interconnect conductive structure,

wherein the second edge of the third interconnect conductive structure is substantially straight and is oriented substantially parallel to the lengthwise centerline of the third interconnect conductive structure,

wherein the third interconnect conductive structure has a length measured along its lengthwise centerline from its first end to its second end,

wherein the third interconnect conductive structure has a width measured in the first direction perpendicular to the second direction at a midpoint of the lengthwise centerline of the third interconnect conductive structure,

wherein the region includes a fourth interconnect conductive structure positioned in the same interconnect level as the first, second, and third interconnect conductive structures,

the fourth interconnect conductive structure having a top surface, an entirety of a periphery of the top surface of the fourth interconnect conductive structure defined by a first end of the fourth interconnect conductive structure, a second end of the fourth interconnect conductive structure, a first edge of the fourth interconnect conductive structure, and a second edge of the fourth interconnect conductive structure, such that a total distance along the entirety of the periphery of the top surface of the fourth interconnect conductive structure is equal to a sum of a total distance along the first edge of the fourth interconnect conductive structure and a total distance along the second edge of the fourth interconnect conductive structure and a total distance along the first end of the fourth interconnect conductive structure and a total distance along the second end of the fourth interconnect conductive structure,

wherein the total distance along the first edge of the fourth interconnect conductive structure is greater than two times the total distance along the first end of the fourth interconnect conductive structure,

wherein the total distance along the first edge of the fourth interconnect conductive structure is greater than two times the total distance along the second end of the fourth interconnect conductive structure,

wherein the total distance along the second edge of the fourth interconnect conductive structure is greater than two times the total distance along the first end of the fourth interconnect conductive structure,

wherein the total distance along the second edge of the fourth interconnect conductive structure is greater than two times the total distance along the second end of the fourth interconnect conductive structure,

wherein the first end of the fourth interconnect conductive structure extends from the first edge of the fourth interconnect conductive structure to the second edge of the fourth interconnect conductive structure and is located principally within a space between the first and second edges of the fourth interconnect conductive structure,

wherein the second end of the fourth interconnect conductive structure extends from the first edge of the fourth interconnect conductive structure to the second edge of the fourth interconnect conductive structure and is located principally within the space between the first and second edges of the fourth interconnect conductive structure,

the fourth interconnect conductive structure having a lengthwise centerline oriented in the second direction along its top surface and extending from its first end to its second end,

wherein the first edge of the fourth interconnect conductive structure is substantially straight and is oriented substantially parallel to the lengthwise centerline of the fourth interconnect conductive structure,

wherein the second edge of the fourth interconnect conductive structure is substantially straight and is oriented substantially parallel to the lengthwise centerline of the fourth interconnect conductive structure,

wherein the fourth interconnect conductive structure has a length measured along its lengthwise centerline from its first end to its second end,

wherein the fourth interconnect conductive structure has a width measured in the first direction perpendicular to the second direction at a midpoint of the lengthwise centerline of the fourth interconnect conductive structure,

wherein the third and fourth interconnect conductive structures are positioned next to and spaced apart from each other such that a distance as measured in the first direction between their lengthwise centerlines is substantially equal to the second pitch.

11. The semiconductor chip as recited in claim 10, wherein at least one of the at least eight conductive structures within the region does not form a gate electrode of any transistor and has a width as measured in the second direction that is substantially equal to a width as measured in the second direction of another of the at least eight conductive structures.

12. The semiconductor chip as recited in claim 11, wherein the first, second, and third interconnect conductive structures are positioned within either of the first interconnect level, the second interconnect level, or the third interconnect level.

13. The semiconductor chip as recited in claim 1, wherein at least one of the at least eight conductive structures is positioned at the first pitch away from the second conductive structure such that its lengthwise centerline is separated from the lengthwise centerline of the second conductive structure by the first pitch as measured in the second direction and such that at least a portion of its length is next to at least a portion of the length of the second conductive structure,

wherein a total length as measured in the first direction of the at least one of the at least eight conductive structures that is positioned at the first pitch away from the second conductive structure is substantially equal to the total length of the second conductive structure as measured in the first direction,

wherein the region includes a third conductive structure of the at least eight conductive structures, the third conductive structure positioned so that at least a portion of its length is next to at least a portion of the length of the at least one of the at least eight conductive structures that is positioned at the first pitch away from the second conductive structure, the third conductive structure positioned such that a distance as measured in the second direction between its lengthwise centerline and the lengthwise centerline of the at least one of the at least eight conductive structures that is positioned at the first pitch away from the second conductive structure is substantially equal to the first pitch, and

wherein a total length of the third conductive structure as measured in the first direction is substantially equal to the total length of the second conductive structure as measured in the first direction.

14. The semiconductor chip as recited in claim 13, wherein the at least one of the at least eight conductive structures that is positioned at the first pitch away from the second conductive structure is the conductive structure that forms the gate electrode of the second transistor of the second transistor type.

15. The semiconductor chip as recited in claim 14, wherein the third conductive structure forms at least one gate electrode of at least one transistor.

16. The semiconductor chip as recited in claim 1, wherein the region includes a third transistor of the first transistor type, a fourth transistor of the first transistor type, a third transistor of the second transistor type, and a fourth transistor of the second transistor type,

the third transistor of the first transistor type having a gate electrode formed by a portion of a third conductive structure of the at least eight conductive structures, the third transistor of the second transistor type having a gate electrode formed by another portion of the third conductive structure,

the fourth transistor of the first transistor type having a gate electrode formed by a portion of a fourth conductive structure of the at least eight conductive structures, the fourth transistor of the second transistor type having a gate electrode formed by another portion of the fourth conductive structure.

17. The semiconductor chip as recited in claim 16, wherein the first transistor of the first transistor type has a first diffusion terminal physically and electrically connected to a first diffusion terminal of the second transistor of the first transistor type, and

wherein the first transistor of the second transistor type has a first diffusion terminal physically and electrically connected to a first diffusion terminal of the second transistor of the second transistor type.

18. The semiconductor chip as recited in claim 17, wherein the region includes a fifth transistor of the first transistor type and a fifth transistor of the second transistor type,

the fifth transistor of the first transistor type having a gate electrode formed by a portion of a fifth conductive structure of the at least eight conductive structures, wherein any transistor having its gate electrode formed by the fifth conductive structure is of the first transistor type,

the fifth transistor of the second transistor type having a gate electrode formed by a portion of a sixth conductive structure of the at least eight conductive structures, wherein any transistor having its gate electrode formed by the sixth conductive structure is of the second transistor type.

19. The semiconductor chip as recited in claim 18,

wherein the lengthwise centerline of the first conductive structure is substantially aligned with the lengthwise centerline of the conductive structure that forms the gate electrode of the second transistor of the second transistor type,

the lengthwise centerline of the fifth conductive structure substantially aligned with the lengthwise centerline of the sixth conductive structure,

the gate electrode of the second transistor of the second transistor type electrically connected to the gate electrode of the fifth transistor of the first transistor type,

the gate electrode of the first transistor of the first transistor type electrically connected to the gate electrode of the fifth transistor of the second transistor type,

the first transistor of the first transistor type having a second diffusion terminal physically and electrically connected to a first diffusion terminal of the fifth transistor of the first transistor type, and

the second transistor of the second transistor type having a second diffusion terminal physically and electrically connected to a first diffusion terminal of the fifth transistor of the second transistor type.

20. The semiconductor chip as recited in claim 19, wherein a first electrical connection electrically connects the gate electrode of the second transistor of the second transistor type to the gate electrode of the fifth transistor of the first transistor type, the first electrical connection including at least one interconnect conductive structure positioned within either of a first interconnect level, a second interconnect level, or a third interconnect level,

the at least one interconnect conductive structure of the first electrical connection having a top surface, an entirety of a periphery of the top surface of the at least one interconnect conductive structure of the first electrical connection defined by a first end of the at least one interconnect conductive structure of the first electrical connection, a second end of the at least one interconnect conductive structure of the first electrical connection, a first edge of the at least one interconnect conductive structure of the first electrical connection, and a second edge of the at least one interconnect conductive structure of the first electrical connection, such that a total distance along the entirety of the periphery of the top surface of the at least one interconnect conductive structure of the first electrical connection is equal to a sum of a total distance along the first edge of the at least one interconnect conductive structure of the first electrical connection and a total distance along the second edge of the at least one interconnect conductive structure of the first electrical connection and a total distance along the first end of the at least one interconnect conductive structure of the first electrical connection and a total distance along the second end of the at least one interconnect conductive structure of the first electrical connection,

wherein the total distance along the first edge of the at least one interconnect conductive structure of the first electrical connection is greater than two times the total distance along the first end of the at least one interconnect conductive structure of the first electrical connection,

wherein the total distance along the first edge of the at least one interconnect conductive structure of the first electrical connection is greater than two times the total distance along the second end of the at least one interconnect conductive structure of the first electrical connection,

wherein the total distance along the second edge of the at least one interconnect conductive structure of the first electrical connection is greater than two times the total distance along the first end of the at least one interconnect conductive structure of the first electrical connection,

wherein the total distance along the second edge of the at least one interconnect conductive structure of the first electrical connection is greater than two times the total distance along the second end of the at least one interconnect conductive structure of the first electrical connection,

wherein the first end of the at least one interconnect conductive structure of the first electrical connection extends from the first edge of the at least one interconnect conductive structure of the first electrical connection to the second edge of the at least one interconnect conductive structure of the first electrical connection, and

wherein the first end of the at least one interconnect conductive structure of the first electrical connection is located principally within the space between the first and second edges of the at least one interconnect conductive structure of the first electrical connection,

wherein the second end of the at least one interconnect conductive structure of the first electrical connection extends from the first edge of the at least one interconnect conductive structure of the first electrical connection to the second edge of the at least one interconnect conductive structure of the first electrical connection, and

wherein the second end of the at least one interconnect conductive structure of the first electrical connection is located principally within the space between the first and second edges of the at least one interconnect conductive structure of the first electrical connection,

the at least one interconnect conductive structure of the first electrical connection having a lengthwise centerline oriented in only one of the first direction and the second direction, the lengthwise centerline of the at least one interconnect conductive structure of the first electrical connection extending along the top surface of the at least one interconnect conductive structure of the first electrical connection and between the first and second ends of the at least one interconnect conductive structure of the first electrical connection,

wherein the first edge of the at least one interconnect conductive structure of the first electrical connection is substantially straight and is oriented substantially parallel to the lengthwise centerline of the at least one interconnect conductive structure of the first electrical connection,

wherein the second edge of the at least one interconnect conductive structure of the first electrical connection is substantially straight and is oriented substantially parallel to the lengthwise centerline of the at least one interconnect conductive structure of the first electrical connection,

wherein the at least one interconnect conductive structure of the first electrical connection has a length measured along its lengthwise centerline from its first end to its second end,

wherein the at least one interconnect conductive structure of the first electrical connection has a width measured in a direction perpendicular to its lengthwise centerline at a midpoint of its lengthwise centerline,

wherein a second electrical connection electrically connects the gate electrode of the first transistor of the first transistor type to the gate electrode of the fifth transistor of the second transistor type, the second electrical connection including at least one interconnect conductive structure positioned within either the first interconnect level, the second interconnect level, or the third interconnect level,

the at least one interconnect conductive structure of the second electrical connection having a top surface, an entirety of a periphery of the top surface of the at least one interconnect conductive structure of the second electrical connection defined by a first end of the at least one interconnect conductive structure of the second electrical connection, a second end of the at least one interconnect conductive structure of the second electrical connection, a first edge of the at least one interconnect conductive structure of the second electrical connection, and a second edge of the at least one interconnect conductive structure of the second electrical connection, such that a total distance along the entirety of the periphery of the top surface of the at least one interconnect conductive structure of the second electrical connection is equal to a sum of a total distance along the first edge of the at least one interconnect conductive structure of the second electrical connection and a total distance along the second edge of the at least one interconnect conductive structure of the second electrical connection and a total distance along the first end of the at least one interconnect conductive structure of the second electrical connection and a total distance along the second end of the at least one interconnect conductive structure of the second electrical connection,

wherein the total distance along the first edge of the at least one interconnect conductive structure of the second electrical connection is greater than two times the total distance along the first end of the at least one interconnect conductive structure of the second electrical connection,

wherein the total distance along the first edge of the at least one interconnect conductive structure of the second electrical connection is greater than two times the total distance along the second end of the at least one interconnect conductive structure of the second electrical connection,

wherein the total distance along the second edge of the at least one interconnect conductive structure of the second electrical connection is greater than two times the total distance along the first end of the at least one interconnect conductive structure of the second electrical connection,

wherein the total distance along the second edge of the at least one interconnect conductive structure of the second electrical connection is greater than two times the total distance along the second end of the at least one interconnect conductive structure of the second electrical connection,

wherein the first end of the at least one interconnect conductive structure of the second electrical connection extends from the first edge of the at least one interconnect conductive structure of the second electrical connection to the second edge of the at least one interconnect conductive structure of the second electrical connection, and

wherein the first end of the at least one interconnect conductive structure of the second electrical connection is located principally within the space between the first and second edges of the at least one interconnect conductive structure of the second electrical connection,

wherein the second end of the at least one interconnect conductive structure of the second electrical connection extends from the first edge of the at least one interconnect conductive structure of the second electrical connection to the second edge of the at least one interconnect conductive structure of the second electrical connection, and

wherein the second end of the at least one interconnect conductive structure of the second electrical connection is located principally within the space between the first and second edges of the at least one interconnect conductive structure of the second electrical connection,

the at least one interconnect conductive structure of the second electrical connection having a lengthwise centerline oriented in only one of the first direction and the second direction, the lengthwise centerline of the at least one interconnect conductive structure of the second electrical connection extending along the top surface of the at least one interconnect conductive structure of the second electrical connection and between the first and second ends of the at least one interconnect conductive structure of the second electrical connection,

wherein the first edge of the at least one interconnect conductive structure of the second electrical connection is substantially straight and is oriented substantially parallel to the lengthwise centerline of the at least one interconnect conductive structure of the second electrical connection,

wherein the second edge of the at least one interconnect conductive structure of the second electrical connection is substantially straight and is oriented substantially parallel to the lengthwise centerline of the at least one interconnect conductive structure of the second electrical connection,

wherein the at least one interconnect conductive structure of the second electrical connection has a length measured along its lengthwise centerline from its first end to its second end,

wherein the at least one interconnect conductive structure of the second electrical connection has a width measured in a direction perpendicular to its lengthwise centerline at a midpoint of its lengthwise centerline,

wherein the first interconnect level is formed at a vertical position within the semiconductor chip above the at least eight conductive structures, wherein the first interconnect level is separated from the co-planar top surfaces of the at least eight conductive structures by at least one dielectric material,

wherein the second interconnect level is formed at a vertical position within the semiconductor chip above the first interconnect level, and

wherein the third interconnect level is formed at a vertical position within the semiconductor chip above the second interconnect level.

21. The semiconductor chip as recited in claim 17, wherein a total length of the third conductive structure as measured in the first direction is substantially equal to the total length of the second conductive structure as measured in the first direction, and

wherein a total length of the fourth conductive structure as measured in the first direction is substantially equal to the total length of the second conductive structure as measured in the first direction.

22. The semiconductor chip as recited in claim 21, wherein at least one of the at least eight conductive structures within the region is a non-gate forming conductive structure that does not form a gate electrode of any transistor,

the non-gate forming conductive structure positioned between at least two other gate forming conductive structures of the at least eight conductive structures, each of the at least two other gate forming conductive structures forming at least one gate electrode of at least one transistor,

the non-gate forming conductive structure positioned such that its lengthwise centerline is separated from the lengthwise centerlines of each of the at least two other gate forming conductive structures by the first pitch as measured in the second direction,

the non-gate forming conductive structure having a width as measured in the second direction that is substantially equal to a width as measured in the second direction of at least one of the at least two other gate forming conductive structures.

23. The semiconductor chip as recited in claim 17, wherein the region includes a first connection forming conductive structure positioned to physically join to the top surface of the first conductive structure of the at least eight conductive structures, wherein the first connection forming conductive structure is positioned a first connection distance away from a nearest gate electrode forming portion of the first conductive structure, the first connection distance measured in the first direction between closest located portions of the first connection forming conductive structure and the nearest gate electrode forming portion of the first conductive structure,

wherein the region includes a second connection forming conductive structure positioned to physically join to the top surface of the second conductive structure of the at least eight conductive structures,

wherein the region includes a third connection forming conductive structure positioned to physically join to the top surface of the third conductive structure of the at least eight conductive structures,

wherein the region includes a fourth connection forming conductive structure positioned to physically join to the top surface of the fourth conductive structure of the at least eight conductive structures,

wherein the region includes a fifth connection forming conductive structure positioned to physically join to the top surface of the conductive structure that forms the gate electrode of the second transistor of the second transistor type, wherein the fifth connection forming conductive structure is positioned a second connection distance away from a nearest gate electrode forming portion of the conductive structure that forms the gate electrode of the second transistor of the second transistor type, the fifth connection distance measured in the first direction between closest located portions of the fifth connection forming conductive structure and the nearest gate electrode forming portion of the conductive structure that forms the gate electrode of the second transistor of the second transistor type, the second connection distance being different from the first connection distance.

24. The semiconductor chip as recited in claim 23, wherein at least two of the at least eight conductive structures have different total lengths as measured in the first direction.

25. The semiconductor chip as recited in claim 24, wherein at least one of the at least eight conductive structures within the region is a non-gate forming conductive structure that does not form a gate electrode of any transistor,

the non-gate forming conductive structure positioned between at least two other gate forming conductive structures of the at least eight conductive structures, each of the at least two other gate forming conductive structures forming at least one gate electrode of at least one transistor,

the non-gate forming conductive structure positioned such that its lengthwise centerline is separated from the lengthwise centerlines of each of the at least two other gate forming conductive structures by the first pitch as measured in the second direction,

the non-gate forming conductive structure having a width as measured in the second direction that is substantially equal to a width as measured in the second direction of at least one of the at least two other gate forming conductive structures.

26. The semiconductor chip as recited in claim 25, wherein the first connection forming conductive structure is substantially centered in the second direction on the first conductive structure of the at least eight conductive structures, the first connection forming conductive structure formed to extend in a vertical direction substantially perpendicular to the substrate of the semiconductor chip from the top surface of the first conductive structure through a dielectric material to contact at least one interconnect conductive structure,

wherein the second connection forming conductive structure is substantially centered in the second direction on the second conductive structure of the at least eight conductive structures, the second connection forming conductive structure formed to extend in the vertical direction substantially perpendicular to the substrate of the semiconductor chip from the top surface of the second conductive structure through the dielectric material to contact at least one interconnect conductive structure,

wherein the third connection forming conductive structure is substantially centered in the second direction on the third conductive structure of the at least eight conductive structures, the third connection forming conductive structure formed to extend in the vertical direction substantially perpendicular to the substrate of the semiconductor chip from the top surface of the third conductive structure through the dielectric material to contact at least one interconnect conductive structure,

wherein the fourth connection forming conductive structure is substantially centered in the second direction on the fourth conductive structure of the at least eight conductive structures, the fourth connection forming conductive structure formed to extend in the vertical direction substantially perpendicular to the substrate of the semiconductor chip from the top surface of the fourth conductive structure through the dielectric material to contact at least one interconnect conductive structure, and

wherein the fifth connection forming conductive structure is substantially centered in the second direction on the conductive structure that forms the gate electrode of the second transistor of the second transistor type, the fifth connection forming conductive structure formed to extend in the vertical direction substantially perpendicular to the substrate of the semiconductor chip from the top surface of the conductive structure that forms the gate electrode of the second transistor of the second transistor type through the dielectric material to contact at least one interconnect conductive structure.

27. The semiconductor chip as recited in claim 1, wherein at least one of the at least eight conductive structures within the region is a non-gate forming conductive structure that does not form a gate electrode of any transistor,

the non-gate forming conductive structure positioned between at least two other gate forming conductive structures of the at least eight conductive structures, each of the at least two other gate forming conductive structures forming at least one gate electrode of at least one transistor,

the non-gate forming conductive structure having a width as measured in the second direction that is substantially equal to a width as measured in the second direction of at least one other of the at least eight conductive structures within the region.

28. The semiconductor chip as recited in claim 1, wherein the region includes a first gate contact positioned to physically contact the top surface of the first conductive structure of the at least eight conductive structures, the first gate contact formed to extend in a vertical direction substantially perpendicular to the substrate of the semiconductor chip from the top surface of the first conductive structure through a dielectric material to contact at least one interconnect conductive structure,

wherein the region includes a second gate contact positioned to physically contact the top surface of the second conductive structure of the at least eight conductive structures, the second gate contact formed to extend in the vertical direction substantially perpendicular to the substrate of the semiconductor chip from the top surface of the second conductive structure through the dielectric material to contact at least one interconnect conductive structure,

wherein the region includes a third gate contact positioned to physically contact the top surface of the conductive structure that forms the gate electrode of the second transistor of the second transistor type, the third gate contact formed to extend in the vertical direction substantially perpendicular to the substrate of the semiconductor chip from the top surface of the conductive structure that forms the gate electrode of the second transistor of the second transistor type and through the dielectric material to contact at least one interconnect conductive structure.

29. A method for manufacturing an integrated circuit within a semiconductor chip, comprising:

forming a region within the semiconductor chip that includes a plurality of transistors, each of the plurality of transistors in the region forming part of circuitry associated with execution of one or more logic functions,

the region including at least eight conductive structures, some of the at least eight conductive structures forming at least one transistor gate electrode,

each of the at least eight conductive structures respectively having a corresponding top surface, wherein an entirety of a periphery of the corresponding top surface is defined by a corresponding first end, a corresponding second end, a corresponding first edge, and a corresponding second edge, such that a total distance along the entirety of the periphery of the corresponding top surface is equal to a sum of a total distance along the corresponding first edge and a total distance along the corresponding second edge and a total distance along the corresponding first end and a total distance along the corresponding second end,

wherein the total distance along the corresponding first edge is greater than two times the total distance along the corresponding first end,

wherein the total distance along the corresponding first edge is greater than two times the total distance along the corresponding second end,

wherein the total distance along the corresponding second edge is greater than two times the total distance along the corresponding first end,

wherein the total distance along the corresponding second edge is greater than two times the total distance along the corresponding second end,

wherein the corresponding first end extends from the corresponding first edge to the corresponding second edge and is located principally within a space between the corresponding first and second edges,

wherein the corresponding second end extends from the corresponding first edge to the corresponding second edge and is located principally within the space between the corresponding first and second edges,

the top surfaces of the at least eight conductive structures co-planar with each other,

each of the at least eight conductive structures having a corresponding lengthwise centerline oriented in a first direction along its top surface and extending from its first end to its second end,

each of the at least eight conductive structures having a length as measured along its lengthwise centerline from its first end to its second end,

wherein the first edge of each of the at least eight conductive structures is substantially straight,

wherein the second edge of each of the at least eight conductive structures is substantially straight,

each of the at least eight conductive structures having both its first edge and its second edge oriented substantially parallel to its lengthwise centerline,

each of the at least eight conductive structures having a width measured in a second direction perpendicular to the first direction at a midpoint of its lengthwise centerline,

each of the first direction and the second direction oriented substantially parallel to the co-planar top surfaces of the at least eight conductive structures,

the at least eight conductive structures positioned in a side-by-side manner such that each of the at least eight conductive structures is positioned to have at least a portion of its length located beside at least a portion of the length of another of the at least eight conductive structures,

wherein the width of each of the at least eight conductive structures is less than 45 nanometers, the region having a size of about 965 nanometers as measured in the second direction, each of the at least eight conductive structures positioned such that a distance as measured in the second direction between its lengthwise centerline and the lengthwise centerline of at least one other of the at least eight conductive structures is substantially equal to a first pitch that is less than or equal to about 193 nanometers,

the region including a first transistor of a first transistor type, a second transistor of the first transistor type, a first transistor of a second transistor type, and a second transistor of the second transistor type,

wherein each transistor of the first transistor type having its gate electrode formed by any of the at least eight conductive structures is included in a first collection of transistors, and wherein each transistor of the second transistor type having its gate electrode formed by any of the at least eight conductive structures is included in a second collection of transistors, wherein the first and second collections of transistors are separated from each other by an inner sub-region of the region, wherein the inner sub-region does not include a source or a drain of any transistor,

the first transistor of the first transistor type having a gate electrode formed by a portion of a first conductive structure of the at least eight conductive structures, wherein any transistor having its gate electrode formed by the first conductive structure is of the first transistor type,

the second transistor of the first transistor type having a gate electrode formed by a portion of a second conductive structure of the at least eight conductive structures, the first transistor of the second transistor type having a gate electrode formed by another portion of the second conductive structure, the second conductive structure positioned such that its lengthwise centerline is separated from the lengthwise centerline of the first conductive structure by the first pitch as measured in the second direction,

the second transistor of the second transistor type having a gate electrode formed by one of the at least eight conductive structures, the conductive structure that forms the gate electrode of the second transistor of the second transistor type positioned such that its lengthwise centerline is separated from the lengthwise centerline of the second conductive structure by the first pitch as measured in the second direction, wherein any transistor having its gate electrode formed by the conductive structure that forms the gate electrode of the second transistor of the second transistor type is of the second transistor type,

the first conductive structure having a total length as measured in the first direction that is greater than one-half of a total length of the second conductive structure as measured in the first direction,

the second conductive structure having at least one end substantially positioned at a first reference line oriented in the second direction, and the conductive structure that forms the gate electrode of the second transistor of the second transistor type also having at least one end substantially positioned at the first reference line.

30. The method of claim 29, wherein the region is formed to include a first interconnect conductive structure positioned within either of a first interconnect level, a second interconnect level, a third interconnect level, or a fourth interconnect level,

the first interconnect conductive structure having a top surface, an entirety of a periphery of the top surface of the first interconnect conductive structure defined by a first end of the first interconnect conductive structure, a second end of the first interconnect conductive structure, a first edge of the first interconnect conductive structure, and a second edge of the first interconnect conductive structure, such that a total distance along the entirety of the periphery of the top surface of the first interconnect conductive structure is equal to a sum of a total distance along the first edge of the first interconnect conductive structure and a total distance along the second edge of the first interconnect conductive structure and a total distance along the first end of the first interconnect conductive structure and a total distance along the second end of the first interconnect conductive structure,

wherein the total distance along the first edge of the first interconnect conductive structure is greater than two times the total distance along the first end of the first interconnect conductive structure,

wherein the total distance along the first edge of the first interconnect conductive structure is greater than two times the total distance along the second end of the first interconnect conductive structure,

wherein the total distance along the second edge of the first interconnect conductive structure is greater than two times the total distance along the first end of the first interconnect conductive structure,

wherein the total distance along the second edge of the first interconnect conductive structure is greater than two times the total distance along the second end of the first interconnect conductive structure,

wherein the first end of the first interconnect conductive structure extends from the first edge of the first interconnect conductive structure to the second edge of the first interconnect conductive structure and is located principally within a space between the first and second edges of the first interconnect conductive structure,

wherein the second end of the first interconnect conductive structure extends from the first edge of the first interconnect conductive structure to the second edge of the first interconnect conductive structure and is located principally within the space between the first and second edges of the first interconnect conductive structure,

the first interconnect conductive structure having a lengthwise centerline oriented in the first direction along its top surface and extending from its first end to its second end,

wherein the first edge of the first interconnect conductive structure is substantially straight and is oriented substantially parallel to the lengthwise centerline of the first interconnect conductive structure,

wherein the second edge of the first interconnect conductive structure is substantially straight and is oriented substantially parallel to the lengthwise centerline of the first interconnect conductive structure,

wherein the first interconnect conductive structure has a length measured along its lengthwise centerline from its first end to its second end,

wherein the first interconnect conductive structure has a width measured in the second direction perpendicular to the first direction at a midpoint of the lengthwise centerline of the first interconnect conductive structure,

wherein the first interconnect level is formed at a vertical position within the semiconductor chip above the at least eight conductive structures, wherein the first interconnect level is separated from the co-planar top surfaces of the at least eight conductive structures by at least one dielectric material,

wherein the second interconnect level is formed at a vertical position within the semiconductor chip above the first interconnect level,

wherein the third interconnect level is formed at a vertical position within the semiconductor chip above the second interconnect level, and

wherein the fourth interconnect level is formed at a vertical position within the semiconductor chip above the third interconnect level,

wherein the region is formed to include a second interconnect conductive structure positioned next to and spaced apart from the first interconnect conductive structure in a same interconnect level as the first interconnect conductive structure,

the second interconnect conductive structure having a top surface, an entirety of a periphery of the top surface of the second interconnect conductive structure defined by a first end of the second interconnect conductive structure, a second end of the second interconnect conductive structure, a first edge of the second interconnect conductive structure, and a second edge of the second interconnect conductive structure, such that a total distance along the entirety of the periphery of the top surface of the second interconnect conductive structure is equal to a sum of a total distance along the first edge of the second interconnect conductive structure and a total distance along the second edge of the second interconnect conductive structure and a total distance along the first end of the second interconnect conductive structure and a total distance along the second end of the second interconnect conductive structure,

wherein the total distance along the first edge of the second interconnect conductive structure is greater than two times the total distance along the first end of the second interconnect conductive structure,

wherein the total distance along the first edge of the second interconnect conductive structure is greater than two times the total distance along the second end of the second interconnect conductive structure,

wherein the total distance along the second edge of the second interconnect conductive structure is greater than two times the total distance along the first end of the second interconnect conductive structure,

wherein the total distance along the second edge of the second interconnect conductive structure is greater than two times the total distance along the second end of the second interconnect conductive structure,

wherein the first end of the second interconnect conductive structure extends from the first edge of the second interconnect conductive structure to the second edge of the second interconnect conductive structure and is located principally within a space between the first and second edges of the second interconnect conductive structure,

wherein the second end of the second interconnect conductive structure extends from the first edge of the second interconnect conductive structure to the second edge of the second interconnect conductive structure and is located principally within the space between the first and second edges of the second interconnect conductive structure,

the second interconnect conductive structure having a lengthwise centerline oriented in the first direction along its top surface and extending from its first end to its second end,

wherein the first edge of the second interconnect conductive structure is substantially straight and is oriented substantially parallel to the lengthwise centerline of the second interconnect conductive structure,

wherein the second edge of the second interconnect conductive structure is substantially straight and is oriented substantially parallel to the lengthwise centerline of the second interconnect conductive structure,

wherein the second interconnect conductive structure has a length measured along its lengthwise centerline from its first end to its second end,

wherein the second interconnect conductive structure has a width measured in the second direction perpendicular to the first direction at a midpoint of the lengthwise centerline of the second interconnect conductive structure,

wherein the first and second interconnect conductive structures are positioned such that a distance as measured in the second direction between their lengthwise centerlines is substantially equal to a second pitch, wherein the second pitch is a fractional multiple of the first pitch.