Transition detector

• US 9,444,440 B2
• Filed: 06/30/2011
• Issued: 09/13/2016
• Est. Priority Date: 06/30/2011
• Status: Active Grant

• Current Assignee: STMicroelectronics International N.V. (STMicroelectronics NV)
• Original Assignee: STMicroelectronics International N.V. (STMicroelectronics NV)
• Inventors: Singh, Saurabhkumar, Jain, Abhishek, Chatterjee, Kallol, Parthasarathy, Chittoor
• Primary Examiner(s): Bolourchi, Nader
• Application Number:
  US13/174,574
• Publication Number:
  US 20130003905A1
• Time in Patent Office: 1,902 Days
• Field of Search: 375/360
• US Class Current: 1/1
• CPC Class Codes: H03K 19/00346 Modifications for eliminating interference or parasitic voltages or currents
• CPC Class Codes: H03K 5/1534 Transition or edge detectors

Abstract

An embodiment of a detector includes first and second generators. The first generator is operable to receive a transition of a first signal and to generate in response to the transition a first pulse having a length that is approximately equal to a length of a detection window. And the second generator is operable to receive a second signal and to generate a second pulse having a relationship to the first pulse in response to a transition of the second signal occurring approximately during the detection window.

Claims

1. A transition detector, comprising:

clock-pulse-generation circuitry configured to receive a clock signal and generate a clock pulse comprising a first pair of consecutive opposite logic transitions in response to a single transition edge of the clock signal, said first pair of consecutive opposite logic transitions separated by a length that is approximately equal to a length of a time window that is offset from the single transition edge of the clock signal; and

data-pulse-generation circuitry configured to receive a data signal and generate a data pulse comprising a second pair of consecutive opposite logic transitions in response to a single transition edge of the data signal, the data-pulse-generation circuitry including delay circuitry configured to delay the generation of the data pulse; and

a logic circuit coupled to logically combine the data pulse and the clock pulse in order to detect whether the data pulse and clock pulse simultaneously have a same logic state and generate an output signal in response thereto indicating that the single transition edge of the data signal has occurred within said time window.

2. The transition detector of claim 1 wherein the delay circuitry is configured to delay the data signal by a programmable delay, and wherein the data-pulse-generation circuitry generates the data pulse in response to the delayed data signal.

3. The transition detector of claim 2 wherein the programmable delay is configured to correspond to a time difference between a start of the time window and the single transition edge of the clock signal.

4. The transition detector of claim 1, wherein the clock-pulse-generation circuitry is configured to generate the clock pulse having a pulse width between transitions of the first pair of consecutive opposite logic transitions corresponding to a programmable delay.

5. The transition detector of claim 4 wherein the programmable delay corresponds to a width of the time window.

6. The transition detector of claim 1 wherein the transition detector is configured to have a self-test mode in which the data-pulse-generation circuitry is configured to generate the data pulse in response to said single transition edge of the clock signal.

7. The transition detector of claim 6 further comprising a multiplexer having a first input configured to receive the clock signal and a second input configured to receive the data signal, said multiplexer configured to select the clock signal for application to the data-pulse-generation circuitry in response to the self-test mode.

8. The transition detector of claim 1 wherein the logic circuit is configured to assert said output signal as a flag.

9. The transition detector of claim 8 wherein the logic circuit is further configured to continue to assert the flag until the transition detector is reset.

10. A circuit-implemented method, comprising:

receiving a clock signal;

generating a clock pulse comprising a first pair of consecutive opposite logic transitions in response to a single transition edge of the clock signal, said first pair of consecutive opposite logic transitions separated by a length that is approximately equal to a length of a time window that is offset from the single transition edge of the clock signal;

receiving a data signal;

generating a data pulse comprising a second pair of consecutive opposite logic transitions in response to a single transition edge of the data signal,

wherein said generating the data pulse comprises delaying the generation of the data pulse;

logically combining the data pulse and the clock pulse in order to detect whether the data pulse and clock pulse simultaneously have a same logic state; and

generating an output signal in response to the logical combining indicating that the single transition edge of the data signal has occurred within said time window.

11. The method of claim 10 wherein said output signal indicates detecting a transition of the data signal within the time window if the clock pulse and the data pulse overlap.

12. The method of claim 10 further comprising delaying the data signal by a programmable delay and generating the data pulse in response to the delayed data signal.

13. The method of claim 12 wherein delaying the data signal by the programmable delay comprises delaying the data signal by a time difference between a start of the time window and a clock edge of the clock signal.

14. The method of claim 10, wherein the clock pulse has a pulse width corresponding to a programmable delay.

15. The method of claim 14 wherein the programmable delay corresponds to a width of the time window.

16. The method of claim 10, further comprising generating the data pulse in response to said single transition edge of the clock signal in accordance with a self-test mode of operation.

17. The method of claim 16, further comprising selecting the self-test mode of operation.

18. The method of claim 10, wherein generating the output signal comprises asserting a flag.

19. A detector, comprising:

a first generator configured to receive a first signal and to generate in response to a single transition of the first signal a first pulse comprising a first pair of consecutive opposite logic transitions separated by a length that is approximately equal to a length of a detection window;

a second generator configured to receive a second signal and to generate in response to a single transition of the second signal a second pulse comprising a second pair of consecutive opposite logic transitions; and

an error indicator

coupled to receive the first and second pulses from the first and second generators, respectively,

configured to detect whether the second pulse and the first pulse simultaneously have a same logic state, and

configured to indicate in response to said detection that the single transition of the first signal occurred during said detection window.

20. The detector of claim 19 wherein the first generator includes a delay circuit configured to delay the first signal by approximately the length of the detection window.

21. The detector of claim 19 wherein the first generator includes:

a delay circuit configured to delay the first signal by approximately the length of the detection window; and

a logic gate having a first input node coupled to receive the delayed first signal from the delay circuit and having a second input node coupled to receive the first signal.

22. The detector of claim 19 wherein the first generator includes:

a delay circuit configured to delay the first signal by approximately the length of the detection window; and

a NOR gate having a first input node coupled to receive the delayed first signal from the delay circuit and having a second input node coupled to receive the first signal.

23. The detector of claim 19 wherein the second generator includes a delay circuit configured to delay the second signal by approximately a time from a beginning of the detection window to the single transition of the first signal.

24. The detector of claim 19 wherein the second generator includes a shift circuit configured to shift the second signal such that a portion of the second signal that is aligned with a beginning of the detection window approximately corresponds to a portion of the shifted second signal that is aligned with the single transition of the first signal.

25. The detector of claim 19 wherein the second generator includes:

a first delay circuit configured to delay the second signal by approximately a time from a beginning of the detection window to the single transition of the first signal;

a second delay circuit configured to further delay the delayed second signal from the first delay circuit; and

a logic gate having a first input node coupled to receive the delayed second signal from the first delay circuit and having a second input node coupled to receive the further delayed second signal from the second delay circuit.

26. The detector of claim 19 wherein the second generator includes:

a first delay circuit configured to delay the second signal by approximately a time from a beginning of the detection window to the single transition of the first signal;

a second delay circuit configured to further delay the delayed second signal from the first delay circuit; and

an XOR gate having a first input node coupled to receive the delayed second signal from the first delay circuit and having a second input node coupled to receive the further delayed second signal from the second delay circuit.

27. The detector of claim 19, further including a mode selector configured to configure the second generator to receive the first signal and to generate the second pulse in response to the single transition of the first signal occurring approximately during the detection window.

28. The detector of claim 19, further including a mode selector configured to configure the second generator to receive the first signal and to generate the second pulse in response to the single transition of the first signal.

29. The detector of claim 19, wherein the error indicator includes:

a first logic gate coupled to receive the first and second pulses and a feedback signal, and configured to generate a first intermediate signal;

a second logic gate coupled to receive the first intermediate signal and the feedback signal and configured to generate a second intermediate signal; and

a third logic gate coupled to receive the second intermediate signal and configured to generate an overlap-indication signal.

30. The detector of claim 29 wherein the feedback signal includes the overlap-indication signal.

31. The detector of claim 29, further including a fourth logic gate coupled to receive the overlap-indication signal and configured to generate the feedback signal.

32. The detector of claim 19, wherein the error indicator includes:

a NAND gate coupled to receive the first and second pulses and a feedback signal, and configured to generate a first intermediate signal;

an AND gate coupled to receive the first intermediate signal and the feedback signal and configured to generate a second intermediate signal; and

a NOR gate coupled to receive the second intermediate signal and configured to generate an overlap-indication signal.