Flexible receiver architecture
First Claim
Patent Images
1. A receiver circuit for a data link, the receiver circuit comprising:
- a first signal path including first equalization circuitry;
a second signal path including second equalization circuitry; and
a path selector circuit which selects one signal path of the first and second signal paths and outputs an equalized signal from said one signal path;
a latch circuit which receives said equalized signal from said one signal path and outputs a regenerated serial data signal; and
a serial-input parallel-output circuit which receives the regenerated serial data signal from the latch circuit,wherein the first signal path comprises a decision feedback equalizer circuit and the second signal path comprises linear equalization without decision feedback equalization.
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Abstract
One embodiment relates to a receiver circuit for a data link. The receiver circuit includes at least a first signal path, a second signal path, and a path selector circuit. The first signal path includes first equalization circuitry, and the second signal path includes second equalization circuitry. The path selector circuit is configured to select one signal path of the first and second signal paths. Other embodiments and features are also disclosed.
20 Citations
17 Claims
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1. A receiver circuit for a data link, the receiver circuit comprising:
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a first signal path including first equalization circuitry; a second signal path including second equalization circuitry; and a path selector circuit which selects one signal path of the first and second signal paths and outputs an equalized signal from said one signal path; a latch circuit which receives said equalized signal from said one signal path and outputs a regenerated serial data signal; and a serial-input parallel-output circuit which receives the regenerated serial data signal from the latch circuit, wherein the first signal path comprises a decision feedback equalizer circuit and the second signal path comprises linear equalization without decision feedback equalization. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. An integrated circuit comprising:
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a serial data receiver including multiple signal paths, each signal path including at least one equalization circuit; and a path selector circuit which is configured to select one signal path of the multiple signal paths and outputs an equalized signal from said one signal path; a latch circuit which receives said equalized signal from said one signal path and outputs a regenerated serial data signal; and a serial-input parallel-output circuit which receives the regenerated serial data signal from the latch circuit, wherein a first signal path of the multiple signal path comprises a decision feedback equalizer circuit, and a second signal path of the multiple signal path comprises linear equalization without decision feedback equalization. - View Dependent Claims (11, 12, 13, 14)
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15. A method of receiver equalization, the method comprising:
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providing an integrated circuit with a multiple-path receiver equalizer and a path selector circuit; performing electronic programming to configure the path selector circuit to use a selected signal path for receiver equalization; and performing equalization on received data using the selected signal path and outputting an equalized signal from the selected signal path; latching said equalized signal and outputting a regenerated serial data signal; and converting the regenerated serial data signal to a parallel signal, wherein a first signal path of the multiple-path receiver comprises a decision feedback equalization circuit and a second signal path of the multiple-path receiver comprises linear equalization without decision feedback equalization. - View Dependent Claims (16, 17)
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Specification