Dynamic configuration of processing modules in a network communications processor architecture

• US 9,444,757 B2
• Filed: 07/27/2011
• Issued: 09/13/2016
• Est. Priority Date: 04/27/2009
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Pekcan, Hakan I., Pollock, Steven J., Pirog, Jerry
• Primary Examiner(s): MANSFIELD, THOMAS L
• Application Number:
  US13/192,140
• Publication Number:
  US 20110289179A1
• Time in Patent Office: 1,875 Days
• Field of Search: 370/411
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/084 with a shared cache
• CPC Class Codes: H04L 47/522 Dynamic queue service slot or variable bandwidth allocation
• CPC Class Codes: H04L 47/622 Queue service order
• CPC Class Codes: H04L 49/65 Re-configuration of fast packet switches

Abstract

Described embodiments provide a method of updating configuration data of a network processor having one or more processing modules and a shared memory. A control processor of the network processor writes updated configuration data to the shared memory and sends a configuration update request to a configuration manager. The configuration update request corresponds to the updated configuration data. The configuration manager determines whether the configuration update request corresponds to settings of a given one of the processing modules. If the configuration update request corresponds to settings of a given one of the one or more processing modules, the configuration manager, sends one or more configuration operations to a destination one of the processing modules corresponding to the configuration update request and updated configuration data. The destination processing module updates one or more register values corresponding to configuration settings of the processing module with the corresponding updated configuration data.

Claims

1. A method of updating configuration data of a network computer processor implemented in an integrated circuit chip, the network computer processor having a control processor, one or more hardware accelerators, and at least one shared memory shared between the control processor and one or more hardware accelerators, the method comprising:

writing, by the control processor of the network computer processor, updated configuration data to the at least one shared memory;

sending, by the control processor, a configuration update request to one or more of the hardware accelerators, wherein the configuration update request corresponds to updated configuration data stored in the at least one share memory;

determining whether the configuration update request corresponds to settings of a given one of the hardware accelerators;

when the configuration update request corresponds to settings of a given one of the hardware accelerators;

updating, by a destination accelerator, one or more register values corresponding to configuration settings of the accelerator with the corresponding updated configuration data of the configuration operations;

otherwise, when the configuration update request corresponds to configuration data stored in the at least one shared memory;

performing, by a combination of multiple parallel processing operations in the at least one shared memory, a coherent memory update operation corresponding to the configuration data stored in the at least one shared memory; and

updating one or more task templates of the network computer processor stored in the at least one shared memory, each task template corresponding to a virtual pipeline of the network computer processor, the virtual pipeline defining a processing order of a task through one or more of the hardware accelerators.

2. The method of claim 1, wherein the step of performing a coherent memory update operation corresponding to the configuration data stored in the at least one shared memory further comprises:

sending a coherent memory update request to an accelerator;

if the coherent memory update is a read update;

reading, by the accelerator, modified data corresponding to the coherent memory update from a memory line of the at least one shared memory

otherwise, if the coherent memory update is a write update;

performing, by the accelerator, a read-modify-write operation to the at least one shared memory, wherein the read-modify-write operation comprises (i) maintaining data in entries of a memory line of the at least one memory that include data modified by the control processor, and (ii) writing data corresponding to the coherent memory update request to entries in the memory line that include unmodified data.

3. The method of claim 1, wherein, if the configuration update request corresponds to configuration data stored in the at least one shared memory, the method further comprises:

updating one or more pointers stored in the at least one shared memory, wherein the pointers correspond to producer-consumer queues (PCQs).

4. The method of claim 1, wherein the step of sending a configuration update request further comprises:

writing, by the control processor, (i) updated configuration data to the at least one shared memory, the updated configuration data corresponding to the configuration update request, and (ii) one or more pointers corresponding to the updated configuration data to a producer-consumer queue (PCQ), wherein each pointer corresponds to an address of the updated configuration data stored in the at least one shared memory.

5. The method of claim 1, wherein the configuration update request is communicated over a coherent communications bus of the network computer processor, and wherein the one or more configuration operations are communicated over a ring communication bus of the network processor.

6. A non-transitory machine-readable medium, having encoded thereon program code, wherein, when the program code is executed by a machine, the machine implements a method of updating configuration data of a network computer processor implemented in an integrated circuit chip, the network computer processor having a control processor, one or more accelerators and at least one shared memory, the method comprising:

writing, by the control processor of the network computer processor, updated configuration data to the at least one shared memory;

sending, by the control processor, a configuration update request to one or more of the hardware accelerators, wherein the configuration request corresponds to updated configuration data stored in the at least one shared memory;

determining whether the configuration update request corresponds to settings of a given one of the hardware accelerators;

when the configuration update request corresponds to settings of a given one of the hardware accelerators;

updating, by a destination accelerator, one or more register values corresponding to configuration settings of the accelerator with the corresponding updated configuration data of the configuration operations;

otherwise, when the configuration update request corresponds to configuration data stored in the at least one shared memory;

performing, by a combination of multiple parallel processing operations in the at least one shared memory, a coherent memory update operation corresponding to the configuration data stored in the at least one shared memory; and

updating one or more task templates of the network computer processor stored in the at least one shared memory, each task template corresponding to a virtual pipeline of the network computer processor, the virtual pipeline defining a processing order of a task through one or more of the hardware accelerators,

wherein the configuration update request is communicated over a coherent communications bus of the network computer processor, and wherein the one or more configuration operations are communicated over a ring communication bus of the network computer processor.

7. The non-transitory machine-readable medium of claim 6, wherein the step of performing a coherent memory update operation corresponding to the configuration data stored in the at least one shared memory further comprises:

sending a coherent memory update request to an accelerator;

if the coherent memory update is a read update;

reading, by the accelerator, modified data corresponding to the coherent memory update from a memory line of the at least one shared memory

otherwise, if the coherent memory update is a write update;

performing, by the accelerator, a read-modify-write operation to the at least one shared memory, wherein the read-modify-write operation comprises (i) maintaining data in entries of a memory line of the at least one memory that include data modified by the control processor, and (ii) writing data corresponding to the coherent memory update request to entries in the memory line that include unmodified data.

8. The non-transitory machine-readable storage medium of claim 6, wherein, if the configuration update request corresponds to configuration data stored in the at least one shared memory, the method further comprises:

updating one or more pointers stored in the at least one shared memory, wherein the pointers correspond to one or more producer-consumer queues (PCQs).

9. The non-transitory machine-readable storage medium of claim 6, wherein the step of sending a configuration update request further comprises:

writing, by the control processor, (i) updated configuration data to the at least one shared memory, the updated configuration data corresponding to the configuration update request, and (ii) one or more pointers corresponding to the updated configuration data to a producer-consumer queue (PCQ), wherein each pointer corresponds to an address of the updated configuration data stored in the at least one shared memory.

10. A network computer processor implemented in an integrated circuit chip, the network computer processor comprising:

at least one shared memory;

one or more hardware accelerators;

one or more control processors configured to (i) provide updated configuration data to the at least one shared memory, (ii) send a configuration update request to a configuration manager of the network processor, wherein the configuration update request corresponds to updated configuration data stored in the at least one shared memory;

wherein the configuration manager is configured to determine whether the configuration update request corresponds to settings of a given one of the one or more hardware accelerators;

when the configuration update request corresponds to settings of a given one of the one or more hardware accelerators;

the configuration manager is further configured to send one or more configuration operations to a destination one of the one or more hardware accelerators, wherein the one or more configuration operations correspond to the configuration update request and updated configuration data; and

the destination processing module is configured to update one or more register values corresponding to configuration settings of the hardware accelerator with the corresponding updated configuration data of the one or more configuration operations;

otherwise, when the configuration update request corresponds to configuration data stored in the at least one shared memory;

the configuration manager is further configured to (i) send one or more configuration operations to a destination one of the one or more hardware accelerators, wherein the one or more configuration operations correspond to the configuration update request and data stored in the destination hardware accelerator, and (ii) perform, by a combination of multiple parallel processing operations in the at least one shared memory, a coherent memory update operation corresponding to the configuration data stored in the at least one shared memory,

wherein the control processor is configured to update one or more task templates of the network computer processor stored in the at least one shared memory, each task template corresponding to a virtual pipeline of the network computer processor, the virtual pipeline defining a processing order of a task through one or more of the hardware accelerators.

11. The network computer processor of claim 10, wherein:

the control processor is further configured to (i) write updated configuration data to the at least one shared memory, the updated configuration data corresponding to the configuration update request, and (ii) write one or more pointers corresponding to the updated configuration data to a producer-consumer queue (PCQ) of the configuration manager, wherein each pointer corresponds to an address of the updated configuration data stored in the at least one shared memory; and

the configuration manager is further configured to (i) update one or more pointers stored in the at least one shared memory, wherein the pointers correspond to one or more PCQs of the configuration manager, (ii) update one or more task templates of the network computer processor stored in the at least one shared memory, wherein each task template corresponds to a virtual pipeline of the network processor, the virtual pipeline defining a processing order of a task through one or more of the one or more hardware accelerators, (iii) read the updated configuration data from the at least one shared memory based on the one or more pointers in the PCQ, (iv) group the updated configuration data into one or more configuration operations, and (v) provide the one or more configuration operations to the destination hardware accelerator.

12. The network computer processor of claim 10, wherein the configuration manager comprises:

a logic unit configured to control operation of the configuration manager, the logic unit comprising;

(i) at least one finite state machine, (ii) a data buffer configured to temporarily store the updated configuration data read from the at least one shared memory, and (iii) one or more producer-consumer queues (PCQs) configured to store pointers to updated configuration data in the at least one shared memory;

an interface to the at least one shared memory through a switch of the network computer processor;

an interface to at least one ring communications bus of the network computer processor, the at least one ring communications bus coupled to the one or more processing modules;

an interface to at least one coherent processor bus of the network computer processor, the coherent processor bus coupled to the at least one control processor;

an interrupt interface to the at least one control processor of the network computer processor, the interrupt interface configured to generate interrupts to the control processor based on one or more configuration operations;

and a debug interface configured to transfer debugging data between and a debugging device external to the network processor,

wherein the configuration update request is communicated from the at least one control processor to the configuration manager over the coherent processor bus, and wherein the one or more configuration operations are communicated from the configuration manager to the one or more hardware accelerators over the at least one ring communication bus.

13. The network processor of claim 10, wherein the one or more control processors comprise Reduced Instruction Set Computing (RISC) central processing units (CPUs).

14. The network computer processor of claim 10, wherein the at least one shared memory comprises at least one of an embedded DRAM and a double data rate (DDR) DRAM coupled to the network processor.