Array substrate and manufacturing method thereof, and display device

• US 9,461,075 B2
• Filed: 11/18/2014
• Issued: 10/04/2016
• Est. Priority Date: 06/18/2014
• Status: Active Grant

• Current Assignee: Beijing BOE Display Technology Co Ltd (BOE Technology Group Co., Ltd.), BOE Technology Group Co., Ltd.
• Original Assignee: Beijing BOE Display Technology Co Ltd (BOE Technology Group Co., Ltd.), BOE Technology Group Co., Ltd.
• Inventors: Yu, Haifeng, Huang, Haiqin, Liu, Jiarong
• Primary Examiner(s): Lebentritt, Michael
• Application Number:
  US14/762,029
• Publication Number:
  US 20160254273A1
• Time in Patent Office: 686 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G02F 1/133345 Insulating layers G02F1/1335, G02F1/1337, G02F1/135, G02F1/136 take precedence
• CPC Class Codes: G02F 1/134309 characterised by their geometrical arrangement
• CPC Class Codes: G02F 1/134372 for fringe field switching [FFS] where the common electrode is not patterned
• CPC Class Codes: G02F 1/136227 Through-hole connection of the pixel electrode to the active element through an insulation layer
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G02F 1/13629 Multilayer wirings
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: G02F 2201/121 common or background
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1259 Multistep manufacturing methods

Abstract

The present invention provides an array substrate and a manufacturing method thereof, and a display device, which can solve the problem of RC signal delay caused by large resistance of the common electrode. The array substrate comprises a pixel electrode, a common electrode provided above the pixel electrode, and a common electrode line electrically connected to the common electrode, the pixel electrode and the common electrode are insulated from each other, the array substrate further comprises a first resistance wire layer provided on and in contact with the common electrode line; and a second resistance wire layer provided above and insulated from the first resistance wire layer, the second resistance wire layer is electrically connected to the common electrode line through a via hole penetrating through the first resistance wire layer and an insulation layer provided between the first resistance wire layer and the second resistance wire layer.

Claims

1. An array substrate comprising a pixel electrode, a common electrode provided above the pixel electrode, and a common electrode line electrically connected to the common electrode, wherein the pixel electrode and the common electrode are insulated from each other, and wherein the array substrate further comprises a first resistance wire layer, and a second resistance wire layer which is provided above the first resistance wire layer and is insulated from the first resistance wire layer,

the first resistance wire layer is provided on and in contact with the common electrode line;

and

the second resistance wire layer is electrically connected to the common electrode line through a via hole penetrating through the first resistance wire layer and an insulation layer provided between the first resistance wire layer and the second resistance wire layer.

2. The array substrate of claim 1, wherein the first resistance wire layer and the pixel electrode are provided in the same layer, spaced apart from each other, and made of the same material.

3. The array substrate of claim 1, wherein the second resistance wire layer and the common electrode are provided in the same layer and made of the same material, and wherein the second resistance wire layer is electrically connected to the common electrode.

4. The array substrate of claim 2, wherein the second resistance wire layer and the common electrode are provided in the same layer and made of the same material, and wherein the second resistance wire layer is electrically connected to the common electrode.

5. The array substrate of claim 1, further comprising a thin film transistor, wherein a source and a drain of the thin film transistor and the data line are provided in the same layer, and the data line is connected to the source, and the data line and the common electrode line are provided in the same layer to be parallel to each other.

6. The array substrate of claim 5, wherein the source and the drain of the thin film transistor, the data line and the common electrode line are made of the same material.

7. A manufacturing method of an array substrate, wherein the array substrate is the array substrate of claim 1, the manufacturing method comprising:

forming a pattern including a common electrode line on a base through a patterning process;

forming a pattern including a first resistance wire layer in contact with the common electrode line on the base subjected to the above step through a patterning process;

forming an insulation layer on the base subjected to the above step;

forming a via hole penetrating through the insulation layer and the first resistance wire layer on the base subjected to the above step through a patterning process; and

forming a pattern including a second resistance wire layer on the base subjected to the above step through a patterning process, so that the second resistance wire layer is connected to the common electrode line through the via hole.

8. The manufacturing method of claim 7, further comprising a step of forming a pattern including a pixel electrode while forming the pattern including the first resistance wire layer in contact with the common electrode line, wherein the pixel electrode and the first resistance wire layer are spaced apart from each other.

9. The manufacturing method of claim 7, further comprising a step of forming a pattern including a common electrode while forming the pattern including the second resistance wire layer, wherein the common electrode is connected to the second resistance wire layer.

10. The manufacturing method of claim 8, further comprising a step of forming a pattern including a common electrode while forming the pattern including the second resistance wire layer, wherein the common electrode is connected to the second resistance wire layer.

11. The manufacturing method of claim 7, further comprising a step of forming a source and a drain of a thin film transistor and a data line while forming the pattern including the common electrode line on the base through the patterning process, wherein the data line is connected to the source, and the data line is parallel to the common electrode line.

12. A display device comprising the array substrate of claim 1.