Resistive cross-point architecture for robust data representation with arbitrary precision

• US 9,466,362 B2
• Filed: 08/12/2015
• Issued: 10/11/2016
• Est. Priority Date: 08/12/2014
• Status: Active Grant

• Current Assignee: Arizona Board of Regents (University of Arizona)
• Original Assignee: Arizona Board of Regents (University of Arizona)
• Inventors: Yu, Shimeng, Cao, Yu, Seo, Jae-sun, Vrudhula, Sarma, Ye, Jieping
• Primary Examiner(s): Pham, Ly D
• Application Number:
  US14/824,782
• Publication Number:
  US 20160049195A1
• Time in Patent Office: 426 Days
• Field of Search: 365/148, 365/158, 365/163
• US Class Current: 1/1
• CPC Class Codes: G11C 13/0002 using resistive RAM [RRAM] elements
• CPC Class Codes: G11C 13/0026 Bit-line or column circuits
• CPC Class Codes: G11C 13/0028 Word-line or row circuits
• CPC Class Codes: G11C 13/003 Cell access
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2213/74 Array wherein each memory cell has more than one access device
• CPC Class Codes: G11C 2213/77 Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring

Abstract

This disclosure relates generally to resistive memory systems. The resistive memory systems may be utilized to implement neuro-inspired learning algorithms with full parallelism. In one embodiment, a resistive memory system includes a cross point resistive network and switchable paths. The cross point resistive network includes variable resistive elements and conductive lines. The conductive lines are coupled to the variable resistive elements such that the conductive lines and the variable resistive elements form the cross point resistive network. The switchable paths are connected to the conductive lines so that the switchable paths are operable to selectively interconnect groups of the conductive lines such that subsets of the variable resistive elements each provide a combined variable conductance. With multiple resistive elements in the subsets, process variations in the conductances of the resistive elements average out. As such, learning algorithms may be implemented with greater precision using the cross point resistive network.

Claims

1. A resistive memory system comprising:

a cross point resistive network comprising variable resistive elements and conductive lines coupled to the variable resistive elements such that the conductive lines and the variable resistive elements form the cross point resistive network; and

a plurality of switchable paths connected to the conductive lines so that the plurality of switchable paths are operable to selectively interconnect a group of the conductive lines such that a set of the variable resistive elements provide a combined variable conductance wherein the plurality of switchable paths are operable to selectively interconnect different combinations of the conductive lines of the variable resistive elements so that the set of the variable resistive elements is reconfigurable as different combinations of the variable resistive elements.

2. The resistive memory system of claim 1 wherein the plurality of switchable paths are operable so as to selectively interconnect the different combinations of the conductive lines of such that the different combinations of the set of the variable resistive elements include a first combination of all of the variable resistive elements and at least one other combination that is a subset of the variable resistive elements.

3. The resistive memory system of claim 1 wherein the plurality of switchable paths are connected to the conductive lines such that the plurality of switchable paths are operable to selectively interconnect subgroups of the conductive lines so that subsets of the variable resistive elements within the cross point resistive network and provide the combined variable conductances, each subset of the variable resistive elements providing a corresponding combined variable conductance of the combined variable conductances.

4. The resistive memory system of claim 3 wherein the plurality of switchable paths are operable to selectively interconnect the subgroups of the conductive lines so that the subsets are reconfigurable as different combinations of the variable resistive elements of the subsets of the variable resistive elements.

5. The resistive memory system of claim 4 wherein the variable resistive elements comprise resistive random access memory (RRAM) elements.

6. The resistive memory system of claim 1 wherein the conductive lines comprise word lines and bit lines, wherein each of the variable resistive elements is coupled between a corresponding one of the word lines and a corresponding one of the bit lines such that the cross point resistive network is a cross point resistive array.

7. The resistive memory system of claim 6 wherein the plurality of switchable paths comprise:

switchable word line interconnection paths, wherein each of the switchable word line interconnection paths is connected between a different pair of the word lines;

switchable bit line interconnection paths, wherein each of the switchable bit line interconnection paths is connected between a different pair of the bit lines; and

wherein each of the switchable word line interconnection paths and the switchable bit line interconnection paths are configured to be opened and closed such that different combinations of subarrays of the variable resistive elements are selectively interconnected so that each of the subarrays of the variable resistive elements provide a corresponding combined variable conductance of a plurality of combined variable conductances provided by the subarrays within the cross point resistive array.

8. The resistive memory system of claim 7 further comprising:

word line control circuitry;

bit line control circuitry; and

wherein the word line control circuitry is configured to generate a word line output onto the word lines and the bit line control circuitry is configured to generate a bit line output onto the bit lines such that each of the plurality of combined variable conductances provided by the subarrays is adjustable in parallel.

9. The resistive memory system of claim 8 wherein the word line control circuitry is configured to generate the word line output as word line voltages that represent a first vector by providing each of the word line voltages with a negative pulse and a positive pulse with pulse durations set in accordance to a corresponding vector value of the first vector.

10. The resistive memory system of claim 9 wherein the bit line control circuitry is configured to generate the bit line output as bit line voltages representing a second vector by providing each of the bit line voltages with a set of pulses such that, for each of the bit line voltages a number of the set of pulses is set in accordance to a corresponding vector value of the second vector.

11. The resistive memory system of claim 10 wherein the bit line control circuitry is configured such that for each of the bit line voltages, the set of pulses comprises a set of positive pulses that at least partially temporally align with the negative pulse of a corresponding one of the word line voltages.

12. The resistive memory system of claim 10 wherein the bit line control circuitry is configured such that for each of the bit line voltages, the set of pulses comprises a set of negative pulses that at least partially temporally align with the positive pulse of a corresponding one of the word line voltages.

13. The resistive memory system of claim 10 wherein the bit line control circuitry is configured such that for each of the bit line voltages, the set of pulses is provided by the bit line control circuitry as a set of positive pulses that at least partially temporally align with the negative pulse of a corresponding one of the word line voltages in response to the corresponding vector value of the second vector being positive, and the set of pulses is provided by the bit line control circuitry a set of negative pulses that at least partially temporally align with the positive pulse of the corresponding one of the word line voltages in response to the corresponding vector value of the second vector being negative.

14. The resistive memory system of claim 7 further comprising:

word line control circuitry configured to generate word line voltages such that each of the word line voltages represents a different value of a vector, and to apply the word line voltages, a different row of the subarrays receives a different one of the word line voltages; and

bit line control circuitry configured to receive bit line currents generated in response to the word line voltages, wherein each of the bit line currents is generated by a different column of the subarrays.

15. The resistive memory system of claim 7 further comprising:

bit line control circuitry configured to generate bit line voltages such that each of the bit line voltages represents a different value of a vector, and to apply the bit line voltages, a different column of the subarrays receives a different one of the bit line voltages; and

word line control circuitry configured to receive word line currents generated in response to the bit line voltages, wherein each of the word line currents is generated by a different row of the subarrays.

16. The resistive memory system of claim 6 wherein the plurality of switchable paths comprise:

a switchable word line interconnection path connected between a pair of the word lines;

a switchable bit line interconnection path connected between a pair of the bit lines; and

wherein the switchable word line interconnection path and the switchable bit line interconnection path are configured to be closed such that the set of the variable resistive elements is a subarray of the variable resistive elements within the cross point resistive array, which provide the combined variable conductance.

17. The resistive memory system of claim 1 further comprising switch control circuitry configured to open and close the plurality of switchable paths.