Semiconductor device and manufacturing method thereof

• US 9,466,756 B2
• Filed: 07/09/2013
• Issued: 10/11/2016
• Est. Priority Date: 08/07/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Sakata, Junichiro, Sakakura, Masayuki, Oikawa, Yoshiaki, Okazaki, Kenichi, Maruyama, Hotaka
• Primary Examiner(s): Woldegeorgis, Ermias
• Assistant Examiner(s): LIU, BENJAMIN T
• Application Number:
  US13/937,561
• Publication Number:
  US 20130302924A1
• Time in Patent Office: 1,190 Days
• Field of Search: 438/30, 438/509, 438/40, 438/42, 438/22
• US Class Current: 1/1
• CPC Class Codes: H01L 21/385 using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1251 comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 33/0041 characterised by field-effect operation

Abstract

An object is to improve reliability of a semiconductor device. A semiconductor device including a driver circuit portion and a display portion (also referred to as a pixel portion) over the same substrate is provided. The driver circuit portion and the display portion include thin film transistors in which a semiconductor layer includes an oxide semiconductor; a first wiring; and a second wiring. The thin film transistors each include a source electrode layer and a drain electrode layer which each have a shape whose end portions are located on an inner side than end portions of the semiconductor layer. In the thin film transistor in the driver circuit portion, the semiconductor layer is provided between a gate electrode layer and a conductive layer. The first wiring and the second wiring are electrically connected in an opening provided in a gate insulating layer through an oxide conductive layer.

Claims

1. A method of manufacturing a semiconductor device, the method comprising steps of:

forming a first gate electrode layer and a second gate electrode layer over a substrate;

forming a gate insulating layer over the first gate electrode layer and the second gate electrode layer;

forming an oxide semiconductor layer over the gate insulating layer;

performing a first heat treatment for reducing a resistivity of the oxide semiconductor layer;

forming a first conductive layer over the oxide semiconductor layer;

forming a first resist mask comprising a first region and a second region with a thickness smaller than a thickness of the first region over the first conductive layer;

etching the first conductive layer and the oxide semiconductor layer to form a first island-shape oxide semiconductor layer overlapped with the first gate electrode layer, a second island-shape oxide semiconductor layer overlapped with the second gate electrode layer, a first island-shape conductive layer over the first island-shape oxide semiconductor layer and a second island-shape conductive layer over the second island-shape oxide semiconductor layer by using the first resist mask;

ashing the first resist mask to form a second resist mask by removing the second region;

etching the first island-shape conductive layer and the second island-shape conductive layer to form a first source electrode layer electrically connected to the first island-shape oxide semiconductor layer, a first drain electrode layer electrically connected to the first island-shape oxide semiconductor layer, a second source electrode layer electrically connected to the second island-shape oxide semiconductor layer and a second drain electrode layer electrically connected to the second island-shape oxide semiconductor layer by using the second resist mask;

forming an oxide insulating layer over the first island-shape oxide semiconductor layer, the second island-shape oxide semiconductor layer, the first source electrode layer, the first drain electrode layer, the second source electrode layer and the second drain electrode layer;

performing a second heat treatment on the first island-shape oxide semiconductor layer, the second island-shape oxide semiconductor layer, and the oxide insulating layer;

forming a transparent conductive film over the oxide insulating layer;

etching the transparent conductive film to form a pixel electrode layer electrically connected to the second drain electrode layer and a second conductive layer overlapped with the first gate electrode layer; and

forming a liquid crystal layer over the pixel electrode layer;

wherein each of the first island-shape oxide semiconductor layer and the second island-shape oxide semiconductor layer includes a region which is in contact with the oxide insulating layer, and

wherein the resistivity of the region is increased by the second heat treatment.

2. The semiconductor device according to claim 1, wherein the first heat treatment is performed in an atmosphere of nitrogen gas.

3. The semiconductor device according to claim 1, further comprising the steps of:

heating for dehydrating or dehydrogenating the gate insulating layer before the step of forming the oxide semiconductor layer.

4. The semiconductor device according to claim 1, wherein the region is in an oxygen-excess state by the second heat treatment.

5. The semiconductor device according to claim 1, wherein the oxide semiconductor layer is subjected to dehydration or dehydrogenation by the first heat treatment.

6. The semiconductor device according to claim 1, wherein the first heat treatment is performed in a nitrogen atmosphere with an H₂O concentration of 20 ppm or lower.

7. The semiconductor device according to claim 1, wherein a temperature of the first heat treatment is higher than a temperature of the second heat treatment.

8. A method of manufacturing a semiconductor device, the method comprising steps of:

forming a first gate electrode layer and a second gate electrode layer over a substrate;

forming a gate insulating layer over the first gate electrode layer and the second gate electrode layer;

forming an oxide semiconductor layer over the gate insulating layer;

performing a first heat treatment in an atmosphere of an inert gas for reducing a resistivity of the oxide semiconductor layer;

forming a first conductive layer over the oxide semiconductor layer;

forming a first resist mask comprising a first region and a second region with a thickness smaller than a thickness of the first region over the first conductive layer;

etching the first conductive layer and the oxide semiconductor layer to form a first island-shape oxide semiconductor layer overlapped with the first gate electrode layer, a second island-shape oxide semiconductor layer overlapped with the second gate electrode layer, a first island-shape conductive layer over the first island-shape oxide semiconductor layer and a second island-shape conductive layer over the second island-shape oxide semiconductor layer by using the first resist mask;

ashing the first resist mask to form a second resist mask by removing the second region;

etching the first island-shape conductive layer and the second island-shape conductive layer to form a first source electrode layer electrically connected to the first island-shape oxide semiconductor layer, a first drain electrode layer electrically connected to the first island-shape oxide semiconductor layer, a second source electrode layer electrically connected to the second island-shape oxide semiconductor layer and a second drain electrode layer electrically connected to the second island-shape oxide semiconductor layer by using the second resist mask;

forming an oxide insulating layer over the first island-shape oxide semiconductor layer, the second island-shape oxide semiconductor layer, the first source electrode layer, the first drain electrode layer, the second source electrode layer and the second drain electrode layer;

performing a second heat treatment on the first island-shape oxide semiconductor layer, the second island-shape oxide semiconductor layer, and the oxide insulating layer in an atmosphere of an inert gas;

forming a transparent conductive film over the oxide insulating layer;

etching the transparent conductive film to form a pixel electrode layer electrically connected to the second drain electrode layer and a second conductive layer overlapped with the first gate electrode layer; and

forming a liquid crystal layer over the pixel electrode layer,

wherein each of the first island-shape oxide semiconductor layer and the second island-shape oxide semiconductor layer includes a region which is in contact with the oxide insulating layer, and

wherein the resistivity of the region is increased by the second heat treatment.

9. The semiconductor device according to claim 8, wherein the first heat treatment and the second heat treatment are performed in an atmosphere of nitrogen gas.

10. The semiconductor device according to claim 8, further comprising the steps of:

heating for dehydrating or dehydrogenating the gate insulating layer before the step of forming the oxide semiconductor layer.

11. The semiconductor device according to claim 8, wherein the region is in an oxygen-excess state by the second heat treatment.

12. The semiconductor device according to claim 8, wherein the oxide semiconductor layer is subjected to dehydration or dehydrogenation by the first heat treatment.

13. The semiconductor device according to claim 8, wherein the first heat treatment is performed in a nitrogen atmosphere with an H₂O concentration of 20 ppm or lower.

14. The semiconductor device according to claim 8, wherein a temperature of the first heat treatment is higher than a temperature of the second heat treatment.