Memory system and method of reading data thereof

• US 9,478,298 B2
• Filed: 06/23/2014
• Issued: 10/25/2016
• Est. Priority Date: 06/24/2013
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Shin, Hyun-Ho, Lim, Heung-Soo
• Primary Examiner(s): ABRAHAM, ESAW T
• Application Number:
  US14/312,214
• Publication Number:
  US 20140380129A1
• Time in Patent Office: 855 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/34 Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents

Abstract

A method of reading data in a memory system including a non-volatile memory device, includes reading first data stored in a first block using a first read scheme capable of detecting/correcting an error in the first data, and upon determining an uncorrected error in the first data, setting the first block as a first temporary bad block and reading second data stored in the first temporary bad block using a second read scheme different from the first read scheme.

Claims

1. A method of reading data in a memory system including a non-volatile memory device, the method comprising:

reading first data stored in a first block of the non-volatile memory device using a first read scheme in response to a first read command, wherein the first read scheme is capable of detecting/correcting an error in the first data;

upon determining an uncorrected error in the first data, setting the first block as a first temporary bad block, and reading second data stored in the first temporary bad block using a second read scheme different from the first read scheme in response to a second read command, wherein the second read scheme is capable of detecting/correcting an error in the second data;

upon determining an uncorrected error in the second data, setting the first temporary bad block as a bad block; and

reading the first data stored in the first block using one of the first read scheme and the second read scheme according to the setting of the first block in response to the second read command.

2. The method of claim 1, wherein the first read scheme is a hard decision scheme, and the second read scheme is a soft decision scheme.

3. The method of claim 1, further comprising:

programming write data to the first temporary bad block only if a given percentage of the total data storage capacity of the non-volatile memory device is exceeded.

4. The method of claim 1, further comprising:

reading the first data from the first temporary bad block only if a given percentage of total data storage capacity of the non-volatile memory device is exceeded.

5. The method of claim 1, further comprising:

correcting an error in the second data using the second read scheme, and programming the corrected second data to the first temporary bad block; and

reading the corrected second data from the first temporary bad block only if a given percentage of total data storage capacity of the non-volatile memory device is exceeded.

6. The method of claim 1, further comprising:

correcting an error in the second data using the second read scheme; and

thereafter,

copying the corrected second data from the first block to a normal second block.

7. The method of claim 6, further comprising reading the corrected second data stored in the second block, in response to a second read command about the data stored in the first block set as the first temporary bad block.

8. The method of claim 1, wherein in response to a second read command about the data stored in the first block set as the first temporary bad block, the data stored in the first block is read by the second read scheme without reading the data stored in the first block by the first read scheme.

9. A memory system comprising:

a non-volatile memory cell array including memory blocks that store data; and

a memory controller configured to control operation of the non-volatile memory cell array,

wherein the memory controller is configured to

read first data stored in a first block of the non-volatile memory cell array using a first read scheme, the first read scheme is capable of detecting/correcting an error in the first data, and upon determining an uncorrected error in the first data, setting the first block as a first temporary bad block,

read second data stored in the first temporary bad block using a second read scheme different from the first read scheme, the second read scheme is capable of detecting/correcting an error in the second data, and

read the first data stored in the first block using one of the first read scheme and the second read scheme according to the setting of the first block.

10. The memory system of claim 9, wherein the first read scheme is a hard decision scheme, and the second read scheme is a soft decision scheme.

11. The memory system of claim 9, wherein the memory controller is further configured to program write data to the first temporary bad block only if a given percentage of total data storage capacity of the non-volatile memory cell array is exceeded.

12. The memory system of claim 9, wherein the memory controller is further configured to the first read data from the first temporary bad block only if a given percentage of total data storage capacity of the non-volatile memory cell array is exceeded.

13. The memory system of claim 9, wherein the memory controller is further configured to correct an error in the second data using the second read scheme, program the corrected second data to the first temporary bad block, and read the corrected second data from the first temporary bad block only if a given percentage of total data storage capacity of the non-volatile memory cell array is exceeded.

14. The memory system of claim 9, wherein the memory controller is further configured to correct an error in the second data using the second read scheme, and thereafter, copy the corrected second data from the first block to a normal second block.

15. The memory system of claim 9, wherein the non-volatile memory cell array comprises NAND flash memory.