Flash storage controller execute loop

• US 9,483,210 B2
• Filed: 10/07/2015
• Issued: 11/01/2016
• Est. Priority Date: 12/27/2007
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: Olbrich, Aaron K., Prins, Douglas A.
• Primary Examiner(s): Yi, David X
• Assistant Examiner(s): Mercado, Ramon A
• Application Number:
  US14/877,812
• Publication Number:
  US 20160034227A1
• Time in Patent Office: 391 Days
• Field of Search: 711/103
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 13/1657 Access to multiple memories
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1063 Control signal output circuits, e.g. status or busy flags, feedback command signals

Abstract

A storage controller is provided that contains multiple processors. In some embodiments, the storage controller is coupled to a flash memory module having multiple flash memory groups, each flash memory group corresponding to a distinct flash port in the storage controller, each flash port comprising an associated processor. Each processor handles a portion of one or more host commands, including reads and writes, allowing multiple parallel pipelines to handle one or more host commands simultaneously.

Claims

1. A method comprising:

receiving one or more host commands over a host interface circuit in a storage controller from one or more hosts configured to communicate with the storage controller, the storage controller configured to include one or more storage processors and further configured to be coupled to a flash memory module having multiple flash memory groups, each flash memory group corresponding to a distinct flash memory port in the storage controller, each flash memory port having a flash interface processor;

creating with the one or more storage processors a plurality of transfer requests from a host command of the one or more host commands, each respective transfer request to perform a portion of the host command and being associated with a respective data structure, wherein a state variable in the respective data structure indicates a status of the respective transfer request;

for each transfer request of the plurality of transfer requests, assigning the transfer request to a respective worklist associated with a respective flash interface processor of a respective flash memory port, including assigning the plurality of transfer requests to two or more respective worklists associated with two or more flash interface processors of two or more flash memory ports; and

for each flash interface processor that was assigned a respective transfer request in its respective worklist, performing a task associated with the respective transfer request in the respective worklist.

2. The method of claim 1, wherein the host interface circuit is configured to receive a plurality of host commands from a plurality of hosts coupled to the storage controller, the respective worklists including transfer requests corresponding to host commands from at least two of the plurality of hosts.

3. The method of claim 2, further comprising performing coherency checks on the plurality of host commands received from the plurality of hosts.

4. The method of claim 1, wherein performing a task associated with the respective transfer request in the respective worklist comprises:

checking the state variable in the respective data structure associated with the respective transfer request;

when the state variable is set to command, initiating a task associated with the respective transfer request, and updating the state variable in the data structure to indicate a resource is required;

when the state variable indicates the resource is required, checking if the resource is available; and

when the resource is available, setting or returning a value to indicate that the flash memory port is busy, and completing the task associated with the respective transfer request.

5. The method of claim 4, wherein initiating a task associated with the respective transfer request comprises initiating a DMA transfer.

6. The method of claim 1, wherein performing a task associated with the respective transfer request in the respective worklist comprises:

creating with the flash interface processor a plurality of page requests from the transfer request, each page request to perform a portion of the transfer request; and

for each page request of the plurality of page requests, reading from or writing to a segment of the flash memory group indicated by the respective page request, the flash memory group corresponding to the flash memory port having the flash interface processor.

7. A storage controller circuit comprising:

a host interface circuit configured to receive one or more host commands from one or more hosts configured to communicate with the storage controller;

one or more storage processors to process the one or more host commands; and

a plurality of flash memory ports corresponding to a plurality of flash memory groups in a flash memory module, each flash memory port having a flash interface processor;

the one or more storage processors configured to create a plurality of transfer requests from a host command of the one or more host commands, each respective transfer request to perform a portion of the host command and being associated with a respective data structure, wherein a state variable in the respective data structure indicates a status of the respective transfer request;

the one or more storage processors further configured to assign each one of the plurality of transfer requests to a respective worklist associated with a respective flash interface processor of a respective flash memory port, wherein the one or more storage processors are configured to assign the plurality of transfer requests to two or more respective worklists associated with two or more flash interface processors of two or more flash memory ports; and

each of the flash interface processors configured for performing a task associated with the respective transfer request in the respective worklist.

8. The storage controller circuit of claim 7, wherein the host interface circuit is configured to receive a plurality of host commands from a plurality of hosts coupled to the storage controller, the respective worklists including transfer requests corresponding to host commands from at least two of the plurality of hosts.

9. The storage controller circuit of claim 8, further comprising a command parser to perform coherency checks on the plurality of host commands received from the plurality of hosts, wherein the command parser is coupled to the one or more storage processors.

10. The storage controller circuit of claim 7, wherein performing a task associated with the respective transfer request in the respective worklist comprises:

checking the state variable in the respective data structure associated with the respective transfer request;

when the state variable is set to command, initiating a task associated with the respective transfer request, and updating the state variable in the data structure to indicate a resource is required;

when the state variable indicates the resource is required, checking if the resource is available; and

when the resource is available, setting or returning a value to indicate that the flash memory port is busy, and completing the task associated with the respective transfer request.

11. The storage controller circuit of claim 10, wherein initiating a task associated with the respective transfer request comprises initiating a DMA transfer.

12. The storage controller circuit of claim 7, wherein performing a task associated with the respective transfer request in the respective worklist comprises:

creating with the flash interface processor a plurality of page requests from the transfer request, each page request to perform a portion of the transfer request; and

for each page request of the plurality of page requests, reading from or writing to a segment of the flash memory group indicated by the respective page request, the flash memory group corresponding to the flash memory port having the flash interface processor.

13. The storage controller circuit of claim 7, wherein the one or more storage processors further include command distribution logic comprising a plurality of processors configured to create the plurality of transfer requests and to assign the plurality of transfer requests to the respective worklists.

14. The storage controller circuit of claim 7, further comprising a command parser to perform coherency checks on the one or more host commands received from the one or more hosts, wherein the command parser is coupled to the one or more storage processors.