Vector signaling code with improved noise margin

• US 9,509,437 B2
• Filed: 05/13/2015
• Issued: 11/29/2016
• Est. Priority Date: 05/13/2014
• Status: Active Grant

• Current Assignee: Kandou Labs, SA
• Original Assignee: Kandou Labs, SA
• Inventors: Shokrollahi, Amin
• Primary Examiner(s): Washburn, Daniel
• Assistant Examiner(s): Hassan, Sarah
• Application Number:
  US14/711,528
• Publication Number:
  US 20150333940A1
• Time in Patent Office: 566 Days
• Field of Search: 375/240, 341/50
• US Class Current: 1/1
• CPC Class Codes: B41J 2/00 Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed mounting, arrangement or disposition of types or dies B41J1/00
• CPC Class Codes: H03M 5/145 Conversion to or from block codes or representations thereof
• CPC Class Codes: H04J 13/12 Generation of orthogonal codes
• CPC Class Codes: H04L 1/00 Arrangements for detecting or preventing errors in the information received correcting synchronisation H04L7/00
• CPC Class Codes: H04L 1/0041 Arrangements at the transmitter end
• CPC Class Codes: H04L 25/02 Details ; arrangements for supplying electrical power along data transmission lines systems for transmitting signals via power distribution lines H04B3/54
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission
• CPC Class Codes: H04L 25/49 using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems spectral shaping H04L25/03828
• CPC Class Codes: H04L 25/4906 using binary codes
• CPC Class Codes: H04L 25/4917 using multilevel codes

Abstract

Methods are described allowing a vector signaling code to encode multi-level data without the significant alphabet size increase known to cause symbol dynamic range compression and thus increased noise susceptibility. By intentionally restricting the number of codewords used, good pin efficiency may be maintained along with improved system signal-to-noise ratio.

Claims

1. A system comprising:

a plurality of conductors configured to receive a set of input data bits;

a pre-encoder configured to map the set of input data bits into symbols of a pre-code codeword of a pre-code, wherein the pre-code comprises a constrained set of vectors determined from a maximal set of vectors, and wherein the pre-code is associated with a constrained post-transformation alphabet comprising a portion of low magnitude symbol values selected from an unconstrained post-transformation alphabet associated with the maximal set of vectors, wherein each vector in the constrained set has values selected from a constellation of PAM-M values, wherein M is an integer greater than or equal to 3;

an encoder configured to generate a constrained-alphabet codeword of a constrained-alphabet vector signaling code, the constrained-alphabet codeword representing a transformation of the pre-code codeword with a first non-simple orthogonal matrix, wherein the constrained-alphabet codeword comprises symbols of the constrained post-transformation alphabet; and

,

a driver configured to transmit the constrained-alphabet codeword on a multi-wire communication bus.

2. The system of claim 1, wherein each vector in the constrained set comprises N−

1 symbols, and the first non-simple orthogonal matrix has a size of N, wherein N is an integer greater than or equal to 3.

3. The system of claim 2, wherein the unconstrained post-transformation alphabet comprises (N−

1)*(M−

1)+1 possible symbol values.

4. The system of claim 2, wherein M is odd, and wherein each vector in the constrained set comprises k symbols equal to 0, and the constrained post-transformation alphabet comprises (N−

k−

1)*(M−

1)+1 possible symbol values, wherein k is an integer greater than or equal to 1.

5. The system of claim 1, wherein the constrained post-transformation alphabet comprises predetermined low magnitude values selected from the unconstrained post-transformation alphabet.

6. The system of claim 1, wherein the portion of low magnitude symbol values have magnitudes under a predetermined threshold.

7. The system of claim 1, wherein the first non-simple orthogonal matrix is a Hadamard matrix.

8. The system of claim 7, wherein the Hadamard matrix has a size of at least 4.

9. The system of claim 1, further comprising a receiver, the receiver comprising:

a multi-wire communication bus configured to receive the constrained-alphabet codeword;

a linear combination network configured to obtain the pre-code codeword based on a transformation of the constrained-alphabet codeword by a second non-simple orthogonal matrix, the second non-simple orthogonal matrix based on the first non-simple orthogonal matrix; and

,

a detector configured to detect the symbols of the pre-code codeword, and generate a set of output data bits representative of the set of input data bits.

10. The system of claim 9, wherein the detector is a PAM-M detector, the PAM-M detector comprising a plurality of comparators configured to generate a plurality of comparator outputs, each comparator associated with a respective reference voltage of a set of reference voltages, and wherein the plurality of comparator outputs correspond to the output data bits.

11. A method comprising:

receiving a set of input data bits on a plurality of conductors;

mapping the set of input data bits into symbols of a pre-code codeword of a pre-code, the pre-code corresponding to a constrained set of vectors determined from a maximal set of vectors, wherein each vector in the constrained set has values selected from a constellation of PAM-M values, wherein M is an integer greater than or equal to 3;

generating a constrained-alphabet codeword comprising elements of a constrained alphabet, the constrained-alphabet codeword representing a transformation of the pre-code codeword with a non-simple orthogonal matrix, wherein the constrained alphabet comprises a number m of low magnitude symbol values, the number m less than a total number n of symbol values in an unconstrained alphabet generated by transforming the maximal set of vectors with the non-simple orthogonal matrix, and wherein n and m are integers, n greater than 1 and m greater than 2; and

,

transmitting the constrained-alphabet codeword over a multi-wire bus.

12. The method of claim 11, wherein each vector in the constrained set comprises N−

1 symbols, and the first non-simple orthogonal matrix has a size of N, wherein N is an integer greater than or equal to 3.

13. The method of claim 12, wherein the unconstrained alphabet comprises n=(N−

1)*(M−

1)+1 possible symbol values.

14. The method of claim 12, wherein M is odd, and wherein each vector in the constrained set comprises k symbols equal to 0, and the constrained alphabet comprises m=(N−

k−

1)*(M−

1)+1 possible symbol values, wherein k is an integer greater than or equal to 1.

15. The method of claim 11, wherein the constrained alphabet comprises predetermined low magnitude values selected from the unconstrained alphabet.

16. The method of claim 11, wherein each of the m low magnitude symbol values have magnitudes under a predetermined threshold.

17. The method of claim 11, wherein the non-simple orthogonal matrix is a Hadamard matrix.

18. The method of claim 17, wherein the Hadamard matrix has a size of at least 4.

19. The method of claim 11, further comprising:

receiving the constrained-alphabet codeword on a plurality of conductors;

obtaining the pre-code codeword based on a transformation of the constrained-alphabet codeword with a second non-simple orthogonal matrix, the second non-simple orthogonal matrix based on the first non-simple orthogonal matrix; and

,

generating a set of output data bits by a detector, wherein the set of output data bits is generated based on the pre-code codeword, and are representative of the set of input data bits.

20. The method of claim 19, wherein generating the set of output data bits comprises forming a plurality of comparator outputs using a plurality of comparators, each comparator associated with a respective reference voltage of a set of reference voltages.