Semiconductor device and method for producing same

• US 9,520,476 B2
• Filed: 01/24/2013
• Issued: 12/13/2016
• Est. Priority Date: 01/31/2012
• Status: Active Grant

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Miyamoto, Tadayoshi, Ito, Kazuatsu, Mori, Shigeyasu, Miyamoto, Mitsunobu, Ogawa, Yasuyuki, Nakazawa, Makoto, Uchida, Seiichi, Matsuo, Takuya
• Primary Examiner(s): Nguyen, Cuong Q
• Assistant Examiner(s): Kim, Tong-Ho
• Application Number:
  US14/375,912
• Publication Number:
  US 20140361295A1
• Time in Patent Office: 1,419 Days
• Field of Search: 257/43, 438/104
• US Class Current: 1/1
• CPC Class Codes: H01L 21/441 Deposition of conductive or insulating materials for electrodes
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H10K 59/1213 the pixel elements being TFTs

Abstract

A semiconductor device (100A) includes a substrate (2), an oxide semiconductor layer (5) formed on the substrate (2), source and drain electrodes (6s, 6d) electrically connected to the oxide semiconductor layer (5), a first transparent electrode (7) electrically connected to the drain electrode (6d), a dielectric layer (8) formed on the source and drain electrodes (6s, 6d), and a second transparent electrode (9) formed on the dielectric layer (8). The upper and/or lower surface(s) of the first transparent electrode (7) contacts with a reducing insulating layer (8a) with the property of reducing an oxide semiconductor included in the oxide semiconductor layer (5). The second transparent electrode (9) overlaps at least partially with the first transparent electrode (7) via the dielectric layer (8). The oxide semiconductor layer (5) and the first transparent electrode (7) are formed out of the same oxide film.

Claims

1. A semiconductor device comprising:

a substrate;

a gate electrode on the substrate;

a gate insulating layer located over the gate electrode;

an oxide semiconductor layer on the gate insulating layer;

source and drain electrodes electrically connected to the oxide semiconductor layer;

a first transparent electrode electrically connected to the drain electrode, the first transparent electrode being a pixel electrode;

a dielectric layer located over the source and drain electrodes; and

a second transparent electrode on the dielectric layer, wherein

at least a portion of the second transparent electrode overlaps with the first transparent electrode with the dielectric layer interposed between them,

a lower surface of the first transparent electrode contacts with a reducing insulating layer which has a property of reducing an oxide semiconductor included in the oxide semiconductor layer,

the reducing insulating layer does not contact with a channel region of the oxide semiconductor layer, and

the oxide semiconductor layer and the first transparent electrode are made of the same oxide film.

2. The semiconductor device of claim 1, wherein the dielectric layer includes the reducing insulating layer which contacts with the upper surface of the first transparent electrode;

and an oxide insulating layer which contacts with the channel region of the oxide semiconductor layer.

3. The semiconductor device of claim 1, wherein the gate insulating layer includes the reducing insulating layer which contacts with the lower surface of the first transparent electrode;

and an oxide insulating layer which contacts with a lower surface of the oxide semiconductor layer.

4. The semiconductor device of claim 1, wherein

the drain electrode is on the first transparent electrode, and

the first transparent electrode contacts directly with the drain electrode.

5. The semiconductor device of claim 1, wherein when viewed along a normal to the substrate, an end portion of the reducing insulating layer overlaps with the drain electrode.

6. The semiconductor device of claim 1, wherein the oxide film includes In, Ga and Zn.

7. The semiconductor device of claim 1, wherein the oxide semiconductor layer includes an In—

Ga—

Zn—

O based semiconductor.

8. The semiconductor device of claim 1, wherein the reducing insulating layer includes an upper reducing insulating layer which contacts with the upper surface of the first transparent electrode and a lower reducing insulating layer which contacts with the lower surface of the first transparent electrode.

9. A method for fabricating the semiconductor device of claim 1, the method comprising the steps of:

(a) providing the substrate;

(b) forming the gate electrode and the gate insulating layer on the substrate;

(c) forming the oxide semiconductor film on the gate insulating layer;

(d) forming the source and drain electrodes on the oxide semiconductor film;

(e) forming the dielectric layer over the source and drain electrodes;

(f1) forming, either before or after the step (c), a reducing insulating layer which contacts with a portion of the oxide semiconductor film and which has a property of reducing an oxide semiconductor included in the oxide semiconductor film; and

(f2) after the steps (c) and (f1), forming the first transparent electrode in a portion of the oxide semiconductor film which contacts with the reducing insulating layer and also forming the oxide semiconductor layer in the rest of the oxide semiconductor film which has not been reduced; and

(g) forming the second transparent electrode on the dielectric layer, at least a portion of the second transparent electrode overlapping with the first transparent electrode with the dielectric layer interposed between them.

10. The method of claim 9, wherein the reducing insulating layer is a portion of the gate insulating layer, and the step (b) includes the step (f1).

11. The method of claim 9, wherein the reducing insulating layer is a portion of the dielectric layer, and the step (e) includes the step (f1).

12. The method of claim 9, wherein at least one of the dielectric layer and the gate insulating layer includes an oxide insulating layer, and

the oxide insulating layer contacts with the oxide semiconductor layer.

13. The method of claim 9, wherein when viewed along a normal to the substrate, an end portion of the reducing insulating layer overlaps with the drain electrode.

14. The method of claim 9, wherein the oxide semiconductor film includes an In—

Ga—

Zn—

O based semiconductor.