Branch prediction power reduction

• US 9,547,358 B2
• Filed: 04/27/2012
• Issued: 01/17/2017
• Est. Priority Date: 04/27/2012
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Aggarwal, Aneesh, Segelken, Ross, Wasson, Paul
• Primary Examiner(s): Coleman, Eric
• Application Number:
  US13/458,513
• Publication Number:
  US 20130290676A1
• Time in Patent Office: 1,726 Days
• Field of Search: 712/238
• US Class Current: 1/1
• CPC Class Codes: G06F 1/3243 Power saving in microcontroller unit
• CPC Class Codes: G06F 9/30058 Conditional branch instructions
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

In one embodiment, a microprocessor is provided. The microprocessor includes a branch prediction unit. The branch prediction unit is configured to track the presence of branches in instruction data that is fetched from an instruction memory after a redirection at a target of a predicted taken branch. The branch prediction unit is selectively powered up from a powered-down state when the fetched instruction data includes a branch instruction and is maintained in the powered-down state when the fetched instruction data does not include an instruction branch in order to reduce power consumption of the microprocessor during instruction fetch operations.

Claims

1. A microprocessor comprising:

fetch logic configured to interact with instruction memory to retrieve instruction data for execution;

a branch prediction unit operatively coupled with the fetch logic, including;

a branch controller configured to (1) predict that a branch will be taken in an instruction fetched from the instruction memory, and during an instruction fetch of instruction data from a target location of the branch (2) power up the branch prediction unit from a powered-down state when a branch presence indication for the target location of the branch indicates that instruction data stored at the target location includes a branch instruction, and (3) maintain the branch prediction unit in the powered-down state during the instruction fetch of instruction data from the target location when the branch presence indication for the target location of the branch indicate that instruction data stored at the target location does not include a branch instruction.

2. The microprocessor of claim 1, where the branch presence indication is characterized by one or more first branch presence bits that are stored in a buffer of the branch prediction unit, and where the branch controller is configured to in response to a new target location being allocated in the buffer, set second branch presence bits for the new instruction data at the new target location to power up the branch prediction unit during an instruction fetch of the new instruction data from the new target address.

3. The microprocessor of claim 2, further comprising:

a branch prediction validation unit configured to (1) after instruction data at the target location of the branch is fetched from the instruction memory, validate the fetched instruction data for the presence of a branch prediction, (2) if there is no branch instruction in the fetched instruction data, update the second branch presence bits to maintain the branch prediction unit in the powered-down down state during an instruction fetch of instruction data from the target location, or (3) if there is a branch instruction in the fetched instruction data, update the second branch presence bits to power up the branch prediction unit during an instruction fetch of instruction data from the target location.

4. The microprocessor of claim 3, where the branch prediction validation unit is configured to (1) determine whether the branch prediction unit was powered up during an instruction fetch of instruction data from the target location of the branch, (2) if the branch prediction unit was powered down and a branch was detected in the fetched instruction data, re-fetch the branch instruction, and (3) power up the branch prediction unit to look up a branch prediction for the branch instruction in the instruction data at the target location of the branch.

5. The microprocessor of claim 2, where the branch prediction unit includes a branch target buffer that stores target locations for direct branches and the associated branch presence indications.

6. The microprocessor of claim 5, where the branch controller is configured to power up the branch target buffer to look up the branch presence indication and a prediction of target location for the branch instruction.

7. The microprocessor of claim 2, where the branch prediction unit includes an indirect target buffer that stores target locations for indirect branches and the associated branch presence indications.

8. The microprocessor of claim 1, where the branch presence indication indicates a type of branch instruction and the branch controller is configured to power up designated prediction structures within the branch prediction unit from a powered-down state based on the type of branch instruction indicated by the branch presence indication.

9. The microprocessor of claim 1, where the branch prediction unit is powered up or maintained in a powered-down state at the same time as a look up of a data array of an instruction cache that stores the instruction data in the target location of the branch.

10. The microprocessor of claim 1, where the branch presence indication is characterized by two branch presence bits, each of the two branch presence bits representing a different data half of a cacheline associated with the target location of the branch.

11. A method implemented in a microprocessor including instruction memory and a branch prediction unit operatively coupled with the instruction memory, the method comprising:

predicting that a branch will be taken in an instruction fetched from the instruction memory;

looking up a branch presence indication for a target location of the branch that indicates whether instruction data stored at the target location includes a branch instruction;

during an instruction fetch of instruction data from the target location of the branch, powering up the branch prediction unit from a powered-down state when the branch presence indication for the target location of the branch indicates that instruction data stored at the target location includes a branch instruction; and

maintaining the branch prediction unit in the powered-down state during the instruction fetch of instruction data from the target location when the branch presence indication for the target location of the branch indicates that instruction data stored at the target location does not include a branch instruction.

12. The method of claim 11, where the branch presence indication is characterized by one or more first branch presence bits that are stored in a branch target buffer of the branch prediction unit and the method further comprises:

in response to a new target location being allocated in the branch target buffer, setting second branch presence bits for new instruction data at the new target location to power up the branch prediction unit during an instruction fetch of instruction data from the new target location.

13. The method of claim 12, further comprising:

after instruction data at the target location of the branch is fetched from the instruction memory, validating the fetched instruction data for the presence of a branch instruction; and

if there is no branch instruction in the fetched instruction data, updating the second branch presence bits to maintain the branch prediction unit in the powered-down state during an instruction fetch of instruction data from the target location;

or

if there is a branch instruction in the fetched instruction data, update the second branch presence bits to power up the branch prediction unit during an instruction fetch of instruction data from the target location.

14. The method of claim 11, where the branch presence indication indicates a type of branch instruction, and the method comprises:

powering up designated prediction structures within the branch prediction unit from a powered-down state based on the type of branch instruction indicated by the branch presence indication.

15. The method of claim 11, further comprising:

determining whether the branch prediction unit was powered up during an instruction fetch of instruction data from the target location of the branch;

if the branch prediction unit was powered down and a branch was detected in the fetched instruction data, re-fetching the branch instruction; and

powering up the branch prediction unit to look up a branch prediction for the branch instruction in the instruction data at the target location of the branch.

16. The method of claim 11, where the branch prediction unit is powered up or maintained in a powered-down state at the same time as a look up of a data array of an instruction cache that stores the instruction data in the target location of the branch.

17. A microprocessor comprising:

a branch prediction unit comprising;

a buffer configured to store branch presence bits corresponding to each target address of branch instructions that are fetched from an instruction cache, where the branch presence bits indicate whether instruction data stored at a target address includes a branch instruction; and

a branch controller configured to (1) predict that a branch will be taken in an instruction fetched from the instruction cache, during an instruction fetch of instruction data from a target address of the branch, (2) power up the branch prediction unit from a powered down state when branch presence bits for the target address of the branch indicate that instruction data stored at the target address includes a branch instruction to look up a branch prediction for the branch instruction, and (3) maintain the branch prediction unit in the powered-down state during the instruction fetch of instruction data from the target address when the branch presence bits for the target address of the branch indicate that instruction data stored at the target address does not include a branch instruction; and

a branch prediction validation unit configured to (1) after instruction data is fetched from the instruction cache, validate the fetched instruction data for the presence of a branch instruction, (2) if there is no branch instruction in the fetched instruction data, update the branch presence bits to maintain the branch prediction unit in the powered-down state during an instruction fetch of instruction data from the target address, or (3) if there is a branch instruction in the fetched instruction data, update the branch presence bits to power up the branch prediction unit to look up a branch prediction during an instruction fetch of instruction data from the target address.

18. The microprocessor of claim 17, where the branch prediction validation unit is configured to (1) determine whether the branch prediction unit was powered up during an instruction fetch of instruction data from the target address of the branch, (2) if the branch prediction unit was powered down and a branch was detected in the fetched data, re-fetch the branch instruction, and (3) power up the branch prediction unit to look up a branch prediction for the branch instruction in the instruction data at the target address of the branch.

19. The microprocessor of claim 17, the branch presence bits indicate a type of branch instruction, and the branch controller is configured to power up designated prediction structures within the branch prediction unit from a powered-down state based on the type of branch instruction indicated by the branch presence bits.

20. The microprocessor of claim 17, wherein the buffer is a branch target buffer and the branch controller is configured to in response to a new target address being allocated in the branch target buffer, set branch presence bits for new instruction data at the new target address to power up the branch prediction unit to look up a branch prediction during an instruction fetch of instruction data from the new target address.