Branch prediction power reduction

• US 9,552,032 B2
• Filed: 04/27/2012
• Issued: 01/24/2017
• Est. Priority Date: 04/27/2012
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Aggarwal, Aneesh, Segelken, Ross, Koschoreck, Kevin, Wasson, Paul
• Primary Examiner(s): Coleman, Eric
• Application Number:
  US13/458,542
• Publication Number:
  US 20130290640A1
• Time in Patent Office: 1,733 Days
• Field of Search: 712/239, 713/323, 713/324
• US Class Current: 1/1
• CPC Class Codes: G06F 1/32 Means for saving power
• CPC Class Codes: G06F 1/3243 Power saving in microcontroller unit
• CPC Class Codes: G06F 9/30058 Conditional branch instructions
• CPC Class Codes: G06F 9/38 Concurrent instruction execution, e.g. pipeline or look ahead
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

In one embodiment, a microprocessor is provided. The microprocessor includes instruction memory and a branch prediction unit. The branch prediction unit is configured to use information from the instruction memory to selectively power up the branch prediction unit from a powered-down state when fetched instruction data includes a branch instruction and maintain the branch prediction unit in the powered-down state when the fetched instruction data does not include a branch instruction in order to reduce power consumption of the microprocessor during instruction fetch operations.

Claims

1. A microprocessor comprising:

fetch logic configured to interact with instruction memory to retrieve instruction data for execution;

a branch prediction unit operatively coupled with the fetch logic, including;

a branch controller configured to (1) receive a branch presence indication that indicates whether instruction data in a location in the instruction memory includes a branch instruction, during a fetch of the instruction data from the location in the instruction memory, (2) power up the branch prediction unit from a powered-down state when the branch presence indication indicates that the instruction data includes a branch instruction, and (3) maintain the branch prediction unit in the powered-down state during the fetch of the instruction data when the branch presence indication indicates that the instruction data does not include a branch instruction.

2. The microprocessor of claim 1, where the instruction memory includes an instruction cache including a plurality of cachelines and a cache controller that is configured to in response to a cacheline in the instruction cache being filled with instruction data, set the branch presence indication for the cacheline to power up of the branch prediction unit to look up a branch prediction during an instruction fetch of instruction data from the cacheline.

3. The microprocessor of claim 2, further comprising:

a branch prediction validation unit configured to (1) after instruction data is fetched from the cacheline, validate the fetched instruction data for the presence of a branch instruction, and (2) if there is no branch instruction in the fetched instruction data, update the branch presence indication to maintain the branch prediction unit in the powered-down state during an instruction fetch of instruction data from the cacheline.

4. The microprocessor of claim 3, where the branch prediction validation unit is configured to if there is a branch instruction in the fetched instruction data, update the branch presence indication to power up the branch prediction unit to look up a branch prediction during an instruction fetch of instruction data from the cacheline.

5. The microprocessor of claim 4, where the cache controller is configured to if instruction data from the cacheline is fetched due to a redirection, disallow an update of the branch presence indication.

6. The microprocessor of claim 1, where the branch prediction unit is powered up or maintained in a powered-down state in parallel with a look up of a data array in an instruction cache that stores the instruction data.

7. The microprocessor of claim 1, where the branch presence indication is characterized by branch presence bits, and where the instruction memory includes an instruction cache that includes a least-recently-used bits array that includes least-recentlyused bits for each of a plurality of cacheline sets and the branch presence bits, and the least recently-used bits for a cacheline set indicate a least-recently-used way in that cacheline set.

8. The microprocessor of claim 7, where the location in the instruction memory is a most-recently-used way in a designated cacheline set of the instruction cache, and the branch presence bits for the designated cacheline set are fetched prior to an instruction fetch of the instruction data from the most-recently-used way.

9. The microprocessor of claim 1, where the branch presence indication indicates a type of branch instruction and the branch controller is configured to power up designated prediction structures within the branch prediction unit from a powered-down state based on the type of branch instruction indicated by the branch presence bits.

10. The microprocessor of claim 1, where the branch presence indication is characterized by two branch presence bits, each of the two branch presence bits representing a different data half of a cacheline.

11. A method implemented in a microprocessor including a branch prediction unit and instruction memory, the method comprising:

receiving a branch presence indication that indicates whether instruction data in a location in the instruction memory includes a branch instruction;

during a fetch of the instruction data from the location in the instruction memory, powering up the branch prediction unit from a powered-down state when the branch presence indication indicates that the instruction data includes a branch instruction; and

maintaining the branch prediction unit in the powered-down state during the fetch of the instruction data when the branch presence indication indicates that the instruction data does not include a branch instruction.

12. The method of claim 11, where the instruction memory includes an instruction cache including a plurality of cachelines, further comprising:

in response to a cacheline in the instruction cache being filled with instruction data, setting the branch presence indication for the cacheline to power up of the branch prediction unit to look up a branch prediction during an instruction fetch of instruction data from the cacheline.

13. The method of claim 12, further comprising:

after instruction data in the cache line is fetched from the instruction cache, validating the fetched instruction data for the presence of a branch instruction;

if there is no branch instruction in the fetched instruction data, updating the branch presence indication to maintain the branch prediction unit in the powered-down state during an instruction fetch of instruction data from the cacheline; and

if there is a branch instruction in the fetched instruction data, updating the branch presence indication to power up the branch prediction unit to look up a branch prediction during an instruction fetch of instruction data from the cacheline.

14. The method of claim 13, further comprising:

if instruction data from the cacheline is fetched due to a redirection, disallowing an update of the branch presence indication.

15. The method of claim 11, where the branch prediction unit is powered up or maintained in a powered-down state in parallel with a look up of a data array in an instruction cache that stores the instruction data.

16. The method of claim 11, where the branch presence indication indicates a type of branch instruction, further comprising:

powering up designated prediction structures within the branch prediction unit from a powered-down state based on the type of branch instruction indicated by the branch presence indication.

17. The method of claim 11, where receiving the branch presence indication is performed prior to powering up the branch prediction unit or maintaining the branch prediction unit in the powered down state.

18. A method implemented in a microprocessor including an instruction cache and a branch prediction unit, the instruction cache including a plurality of cacheline sets and branch presence bits corresponding to each of the plurality of cacheline sets, where the branch presence bits indicate whether data in a most-recently-used way in a corresponding cacheline set includes a branch instruction, the method comprising:

receiving branch presence bits that indicate whether a cacheline in a designated cacheline set includes a branch instruction;

during an instruction fetch of instruction data from the cacheline, powering up the branch prediction unit from a powered-down state when the branch presence bits indicate that the instruction data from the cacheline includes a branch instruction;

maintaining the branch prediction unit in the powered-down state during the instruction fetch of instruction data from the cacheline when the branch presence bits indicate that the instruction data from the cacheline does not include a branch instruction;

after instruction data in the cache line is fetched from the instruction cache, validating the fetched instruction data for the presence of a branch instruction;

if there is no branch instruction in the fetched instruction data, updating the branch presence bits to maintain the branch prediction unit in the powered-down state during an instruction fetch of instruction data from the cacheline; and

if there is a branch instruction in the fetched instruction data, updating the branch presence bits to power up the branch prediction unit to look up a branch prediction during an instruction fetch of instruction data from the cacheline.

19. The method of claim 18, further comprising:

if instruction data from the cacheline is fetched due to a redirection, disallowing an update of the branch presence bits.

20. The method of claim 18, where the branch presence bits indicate a type of branch instruction, and the method includes:

powering up designated prediction structures within the branch prediction unit from a powered-down state based on the type of branch instruction indicated by the branch presence bits.

21. A method comprising:

maintaining a branch prediction unit in a powered-down state during an instruction fetch of instruction data from an instruction cache based on at least one branch presence bit indicating that the instruction data does not include a branch instruction; and

during a fetch of the instruction data from the instruction cache, powering up the branch prediction unit from a powered-down state when the branch presence indication indicates that the instruction data includes a branch instruction.