Branch prediction power reduction

  • US 9,552,032 B2
  • Filed: 04/27/2012
  • Issued: 01/24/2017
  • Est. Priority Date: 04/27/2012
  • Status: Active Grant
First Claim
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1. A microprocessor comprising:

  • fetch logic configured to interact with instruction memory to retrieve instruction data for execution;

    a branch prediction unit operatively coupled with the fetch logic, including;

    a branch controller configured to (1) receive a branch presence indication that indicates whether instruction data in a location in the instruction memory includes a branch instruction, during a fetch of the instruction data from the location in the instruction memory, (2) power up the branch prediction unit from a powered-down state when the branch presence indication indicates that the instruction data includes a branch instruction, and (3) maintain the branch prediction unit in the powered-down state during the fetch of the instruction data when the branch presence indication indicates that the instruction data does not include a branch instruction.

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