Branch prediction power reduction
First Claim
Patent Images
1. A microprocessor comprising:
- fetch logic configured to interact with instruction memory to retrieve instruction data for execution;
a branch prediction unit operatively coupled with the fetch logic, including;
a branch controller configured to (1) receive a branch presence indication that indicates whether instruction data in a location in the instruction memory includes a branch instruction, during a fetch of the instruction data from the location in the instruction memory, (2) power up the branch prediction unit from a powered-down state when the branch presence indication indicates that the instruction data includes a branch instruction, and (3) maintain the branch prediction unit in the powered-down state during the fetch of the instruction data when the branch presence indication indicates that the instruction data does not include a branch instruction.
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Abstract
In one embodiment, a microprocessor is provided. The microprocessor includes instruction memory and a branch prediction unit. The branch prediction unit is configured to use information from the instruction memory to selectively power up the branch prediction unit from a powered-down state when fetched instruction data includes a branch instruction and maintain the branch prediction unit in the powered-down state when the fetched instruction data does not include a branch instruction in order to reduce power consumption of the microprocessor during instruction fetch operations.
69 Citations
21 Claims
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1. A microprocessor comprising:
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fetch logic configured to interact with instruction memory to retrieve instruction data for execution; a branch prediction unit operatively coupled with the fetch logic, including; a branch controller configured to (1) receive a branch presence indication that indicates whether instruction data in a location in the instruction memory includes a branch instruction, during a fetch of the instruction data from the location in the instruction memory, (2) power up the branch prediction unit from a powered-down state when the branch presence indication indicates that the instruction data includes a branch instruction, and (3) maintain the branch prediction unit in the powered-down state during the fetch of the instruction data when the branch presence indication indicates that the instruction data does not include a branch instruction. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method implemented in a microprocessor including a branch prediction unit and instruction memory, the method comprising:
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receiving a branch presence indication that indicates whether instruction data in a location in the instruction memory includes a branch instruction; during a fetch of the instruction data from the location in the instruction memory, powering up the branch prediction unit from a powered-down state when the branch presence indication indicates that the instruction data includes a branch instruction; and maintaining the branch prediction unit in the powered-down state during the fetch of the instruction data when the branch presence indication indicates that the instruction data does not include a branch instruction. - View Dependent Claims (12, 13, 14, 15, 16, 17)
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18. A method implemented in a microprocessor including an instruction cache and a branch prediction unit, the instruction cache including a plurality of cacheline sets and branch presence bits corresponding to each of the plurality of cacheline sets, where the branch presence bits indicate whether data in a most-recently-used way in a corresponding cacheline set includes a branch instruction, the method comprising:
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receiving branch presence bits that indicate whether a cacheline in a designated cacheline set includes a branch instruction; during an instruction fetch of instruction data from the cacheline, powering up the branch prediction unit from a powered-down state when the branch presence bits indicate that the instruction data from the cacheline includes a branch instruction; maintaining the branch prediction unit in the powered-down state during the instruction fetch of instruction data from the cacheline when the branch presence bits indicate that the instruction data from the cacheline does not include a branch instruction; after instruction data in the cache line is fetched from the instruction cache, validating the fetched instruction data for the presence of a branch instruction; if there is no branch instruction in the fetched instruction data, updating the branch presence bits to maintain the branch prediction unit in the powered-down state during an instruction fetch of instruction data from the cacheline; and if there is a branch instruction in the fetched instruction data, updating the branch presence bits to power up the branch prediction unit to look up a branch prediction during an instruction fetch of instruction data from the cacheline. - View Dependent Claims (19, 20)
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21. A method comprising:
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maintaining a branch prediction unit in a powered-down state during an instruction fetch of instruction data from an instruction cache based on at least one branch presence bit indicating that the instruction data does not include a branch instruction; and during a fetch of the instruction data from the instruction cache, powering up the branch prediction unit from a powered-down state when the branch presence indication indicates that the instruction data includes a branch instruction.
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Specification