Verifying shared memory integrity

• US 9,552,296 B2
• Filed: 03/15/2013
• Issued: 01/24/2017
• Est. Priority Date: 03/15/2013
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Huynh, Duy Q, McKinney, Lyndsi R
• Primary Examiner(s): Rojas, Midys
• Assistant Examiner(s): Wu, Stephanie
• Application Number:
  US13/842,935
• Publication Number:
  US 20140281195A1
• Time in Patent Office: 1,411 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0806 Multiuser, multiprocessor or multiprocessing cache systems
• CPC Class Codes: G06F 12/0813 with a network or matrix configuration
• CPC Class Codes: G06F 12/0815 Cache consistency protocols
• CPC Class Codes: G06F 12/0828 with concurrent directory accessing, i.e. handling multiple concurrent coherency transactions
• CPC Class Codes: G06F 12/0831 using a bus scheme, e.g. with bus monitoring or watching means
• CPC Class Codes: G06F 12/084 with a shared cache
• CPC Class Codes: G06F 12/0842 for multiprocessing or multitasking
• CPC Class Codes: G06F 12/0866 for peripheral storage systems, e.g. disk cache

Abstract

A method, a system and a computer program product including instructions for verification of the integrity of a shared memory using in line coding is provided. It involves an active step wherein multiple bus masters write a corresponding data to a shared memory. After that it also includes a verification step where data entered in the shared memory by multiple bus masters is verified.

Claims

1. A method for verifying an integrity of a coherent shared memory using inline coding, the coherent shared memory comprising a plurality of memory units, the plurality of memory units being accessed by a plurality of bus masters, the method comprising:

performing an active stage step, wherein the active stage step comprises;

writing, by each of the plurality of bus masters, a corresponding data from a cache memory of each bus master to at least one memory unit from the plurality of memory units, wherein each bus master includes a separate cache memory;

updating, within a status database, a status corresponding to the at least one memory unit to a modified state;

in response to performing the active stage step, performing a rewriting stage step comprising rewriting contents of the corresponding data from each cache memory of each of the plurality of bus masters to the at least one memory unit of the plurality of memory units; and

in response to performing the rewriting stage step, performing a verification stage step, wherein the verification stage step comprises;

each of the plurality of bus masters reading back data written by each of the plurality of bus masters, from the at least one memory unit;

comparing the data read back by each of the plurality of bus masters, with an expected data written in the at least one memory unit, wherein the expected data written is substantially similar to the corresponding data, and wherein the expected data is data which has been written by the plurality of bus masters during the active step; and

updating and/or maintaining the status corresponding to the at least one memory unit in the status database to at least one of;

a verified state, on the event of a match being found between the data read back and the expected data written, by at least one of the plurality of bus masters; and

the modified state, on the event of a mismatch between the data read back and the expected data written by at least one of the plurality of bus masters.

2. The method according to claim 1, wherein the plurality of bus masters is any one of a PPC440, PPC464, PPC476 and DMA.

3. The method according to claim 1, wherein the coherent shared memory is any one of a DDR1, DDR2, DDR3 and SRAM memory.

4. The method according to claim 1, wherein the plurality of memory units are any one of 4, 8, 16, 32, 64, 128, 256 or 512 bits.

5. The method according to claim 1, wherein an entry to the status database is a 4, 8, 16, 32, 64, 128, 256, or 512 bits-wide.

16. The method according to claim 1, wherein the plurality of bus masters comprises at least a first one or more bus masters and a second bus master, the method further comprising:

updating and maintaining the status corresponding to the at least one memory unit in the status database to the verified state, on the event of a mismatch between the data read back and the expected data written by at least one of the first one or more bus masters and a match being found between the data read back and the expected data written by the second bus master, wherein the second bus master has most recently written the corresponding data to the at least one memory unit.

19. The method according to claim 1, wherein the data read back by each particular bus master of the plurality of bus masters comprises all data written in all of the plurality of memory units that the particular bus master previously accessed.

6. A system for verifying an integrity of a coherent shared memory using inline coding, the coherent shared memory comprising a plurality of memory units, the plurality of memory units being accessed by a plurality of bus masters, the plurality of bus masters each having a cache memory, the system comprising:

a write module that;

writes, by each of the plurality of bus masters, a corresponding data from a cache memory of each bus master to at least one memory unit from the plurality of memory units; and

in response to writing, by each of the plurality of bus masters, the corresponding data to the at least one memory unit and updating a status corresponding to the at least one memory unit in a status database, rewriting contents of the corresponding data from each cache memory of each of the plurality of bus masters to the at least one memory unit of the plurality of memory units;

a read module that reads back data written by each of the plurality of bus masters, from the at least one memory unit;

a compare module that matches the data read back by each of the plurality of bus masters, with an expected data written in the at least one memory unit, wherein the expected data written is substantially similar to the corresponding data, and wherein the expected data is data which has been written by the plurality of bus masters through the write module; and

an update module that updates and/or maintains the status corresponding to the at least one memory unit in the status database, wherein the update module;

updates the status corresponding to the at least one memory unit in the status database to a modified state when the corresponding data is written by each of the plurality of bus masters;

updates the status database for the at least one memory unit to verified, on the event of a match being found between the data read back and the expected data written, by at least one of the plurality of bus masters; and

maintains the status database for the at least one memory unit to the modified state, on the event of a mismatch being found between the data read back and the expected data written, by at least one of the plurality of bus masters.

7. The system according to claim 6, wherein the plurality of bus masters is any one of a PPC440, PPC464, PPC476, and a DMA.

8. The system according to claim 6, wherein the coherent shared memory is any one of a DDR1, DDR2 or a DDR3 memory.

9. The system according to claim 6, wherein the plurality of memory units are any one of 4, 8, 16, 32, 64, 128, 256, or 512 bits.

10. The system according to claim 6, wherein an entry to the status database is a 4, 8, 16, 32, 64, 128, 256, or 512 bits-wide word.

17. The system according to claim 6, wherein the plurality of bus masters comprises at least a first one or more bus masters and a second bus master, wherein the update module:

updates and maintains the status corresponding to the at least one memory unit in the status database to the verified state, on the event of a mismatch between the data read back and the expected data written by at least one of the first one or more bus masters and a match being found between the data read back and the expected data written by the second bus master, wherein the second bus master has most recently written the corresponding data to the at least one memory unit;

wherein the data read back by each particular bus master of the plurality of bus masters comprises all data written in all of the plurality of memory units that the particular bus master previously accessed.

11. A computer program product comprising a non-transitory computer readable medium, the non-transitory computer readable medium comprising an inline code used for verifying an integrity of a coherent shared memory, the coherent shared memory comprises a plurality of memory units, the plurality of memory units being accessed by a plurality of bus masters, the plurality of bus masters each having a separate cache memory, the computer program product comprising instructions for:

performing an active stage step, wherein the active stage step comprises;

writing, by each of the plurality of bus masters, a corresponding data from a cache memory of each bus master to at least one memory unit from the plurality of memory units;

updating, within a status database, a status corresponding to the at least one memory unit to a modified state;

in response to performing the active stage step, performing a rewriting stage step comprising rewriting contents of the corresponding data from each cache memory of each of the plurality of bus masters to the at least one memory unit of the plurality of memory units; and

in response to performing the rewriting stage step, performing a verification stage step, wherein the verification stage step comprises;

each of the plurality of bus masters reading back data written by each of the plurality of bus masters, from the at least one memory unit;

comparing the data read back by each of the plurality of bus masters, with an expected data written in the at least one memory unit, wherein the expected data written is substantially similar to the corresponding data, and wherein the expected data is data which has been written by the plurality of bus masters during the active step; and

updating and/or maintaining the status corresponding to the at least one memory unit in the status database to at least one of;

a verified state, on the event of a match being found between the data read back and the expected data written, by at least one of the plurality of bus masters; and

the modified state, on the event of a mismatch between the data read back and the expected data written by at least one of the plurality of bus masters.

12. The computer program product of claim 11, wherein the plurality of bus masters is any one of a PPC440, PPC464, PPC476 and a DMA.

13. The computer program product of claim 11, wherein the coherent shared memory is any one of a DDR1, a DDR2, a DDR3 and a SRAM memory.

14. The computer program product of claim 11, wherein the plurality of memory units are any one of 4, 8, 16, 32, 64, 128, 256, or 512 bits.

15. The computer program product of claim 11, wherein an entry to the status database is a 4, 8, 16, 32, 64, 128, 256, or 512 bits-wide word.

18. The computer program product of claim 11, wherein the plurality of bus masters comprises at least a first one or more bus masters and a second bus master, the instructions further comprising instructions for:

updating and maintaining the status corresponding to the at least one memory unit in the status database to the verified state, on the event of a mismatch between the data read back and the expected data written by at least one of the first one or more bus masters and a match being found between the data read back and the expected data written by the second bus master, wherein the second bus master has most recently written the corresponding data to the at least one memory unit;

wherein the data read back by each particular bus master of the plurality of bus masters comprises all data written in all of the plurality of memory units that the particular bus master previously accessed.