Semiconductor memory device including peripheral circuit for performing program and read opeartions and operating method thereof
First Claim
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1. A semiconductor memory device, comprising:
- a memory cell array including a plurality of pages;
a peripheral circuit suitable for performing a program operation and a read operation on the memory cell array; and
a control logic suitable for controlling the peripheral circuit to apply first and second pass voltages respectively to first and second word lines adjacent to a selected word line during a program verify operation or the read operation, wherein the control logic controls the peripheral circuit to apply a third pass voltage, having a lower potential than both the first and second pass voltages, to unselected word lines except for the selected word line and the first and second word lines.
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Abstract
A semiconductor memory device includes a memory cell array including a plurality of pages; a peripheral circuit suitable for performing a program operation and a read operation on the memory cell array; and a control logic suitable for controlling the peripheral circuit to apply first and second pass voltages respectively to first and second word lines adjacent to a selected word line during a program verify operation or the read operation.
7 Citations
14 Claims
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1. A semiconductor memory device, comprising:
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a memory cell array including a plurality of pages; a peripheral circuit suitable for performing a program operation and a read operation on the memory cell array; and a control logic suitable for controlling the peripheral circuit to apply first and second pass voltages respectively to first and second word lines adjacent to a selected word line during a program verify operation or the read operation, wherein the control logic controls the peripheral circuit to apply a third pass voltage, having a lower potential than both the first and second pass voltages, to unselected word lines except for the selected word line and the first and second word lines. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A program operation method of a semiconductor memory device, comprising:
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applying a program voltage to a word line selected from a plurality of word lines coupled to a memory cell array including a plurality of pages; and performing a program verify operation on a page coupled to the selected word line, wherein the program verify operation includes; applying a verify voltage to the selected word line; applying first and second pass voltages respectively to first and second word lines adjacent to the selected word line; and applying a third pass voltage, having a lower potential than both the first and second pass voltages, to unselected word lines except for the selected word line and the first and second word lines among the plurality of word lines. - View Dependent Claims (8, 9, 10)
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11. A read operation method of a semiconductor memory device, comprising:
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applying a read voltage to a word line selected from a plurality of word lines coupled to a memory cell array including a plurality of pages; applying first and second pass voltages that are different respectively to first and second word lines adjacent to the selected word line; and applying a third pass voltage, having a lower potential than both the first and second pass voltages, to unselected word lines except for the selected word line and the first and second word lines among the plurality of word lines. - View Dependent Claims (12, 13, 14)
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Specification