Low-temperature polysilicon membrane and preparation method thereof, thin-film transistor and display device
First Claim
Patent Images
1. A method for preparing a low temperature poly-silicon (LTPS) membrane, comprising:
- forming a pattern of an amorphous silicon (a-Si) layer on a substrate by a patterning process, wherein the a-Si layer comprises a plurality of convex structures and an etched area which is disposed along circumference of the plurality of convex structures and partially etched, and the plurality of convex structures are connected to each other by amorphous silicon in the etched area;
depositing an insulation layer, used for preventing heat loss on a surface of the a-Si layer, on the a-Si layer of the substrate; and
performing excimer laser crystallization (ELC) on the a-Si layer with the insulation layer being on the surface of the a-Si layer and obtaining the LTPS membrane.
1 Assignment
0 Petitions
Accused Products
Abstract
A method for preparing an LTPS membrane, including: forming an amorphous silicon (a-Si) layer (S3) on a substrate (S1) by a patterning process, in which the a-Si layer (S3) comprises a plurality of convex structures (S32) and etched areas (S31) which are disposed along circumference of the plurality of convex structures and partially etched; and performing excimer laser crystallization (ELC) on the a-Si layer (S3) and obtaining the LTPS membrane. A thin-film transistor (TFT) and a display device are further disclosed, which are used for overcoming poor uniformity of the polysilicon membrane prepared by the ELC technology.
10 Citations
14 Claims
-
1. A method for preparing a low temperature poly-silicon (LTPS) membrane, comprising:
-
forming a pattern of an amorphous silicon (a-Si) layer on a substrate by a patterning process, wherein the a-Si layer comprises a plurality of convex structures and an etched area which is disposed along circumference of the plurality of convex structures and partially etched, and the plurality of convex structures are connected to each other by amorphous silicon in the etched area; depositing an insulation layer, used for preventing heat loss on a surface of the a-Si layer, on the a-Si layer of the substrate; and performing excimer laser crystallization (ELC) on the a-Si layer with the insulation layer being on the surface of the a-Si layer and obtaining the LTPS membrane. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
-
-
10. A method for manufacturing a thin film transistor (TFT), comprising:
-
forming a pattern of an a-Si layer on a substrate by a first patterning process, wherein the a-Si layer comprises a plurality of convex structures and an etched area which is disposed along circumference of the plurality of convex structures and partially etched, and the plurality of convex structures are connected to each other by amorphous silicon in the etched area; depositing an insulation layer, used for preventing heat loss on a surface of the a-Si layer, on the a-Si layer of the substrate; performing an ELC process on the a-Si layer with the insulation layer being on the surface of the a-Si layer and obtaining an LTPS membrane; and forming a pattern of an active layer by performing a second patterning process on the LTPS membrane. - View Dependent Claims (11, 12, 13, 14)
-
Specification