Digital automatic gain control

• US 9,559,653 B2
• Filed: 03/25/2013
• Issued: 01/31/2017
• Est. Priority Date: 12/05/2000
• Status: Active Grant

• Current Assignee: K/S HIMPP
• Original Assignee: K/S HIMPP
• Inventors: Kindred, Jon S., Sorensen, Bryant, Wahl, Jerry
• Primary Examiner(s): Mei, Xu
• Application Number:
  US13/849,652
• Publication Number:
  US 20130285747A1
• Time in Patent Office: 1,408 Days
• Field of Search: 381/102, 381104-109, 381/312, 381/320, 381/321, 381/120, 330/278, 330/254, 330/280
• US Class Current: 1/1
• CPC Class Codes: H03G 1/04 Modifications of control circuit to reduce distortion caused by control modifications to reduce influence of variations of internal impedance of amplifying elements caused by control H03F1/08
• CPC Class Codes: H03G 3/3005 in amplifiers suitable for low-frequencies, e.g. audio amplifiers H03G3/32, H03G3/34 take precedence
• CPC Class Codes: H03G 3/301 the gain being continuously variable
• CPC Class Codes: H03G 7/08 incorporating negative feedback
• CPC Class Codes: H04R 25/356 Amplitude, e.g. amplitude shift or compression
• CPC Class Codes: H04R 25/505 using digital signal processing

Abstract

Systems, devices, and methods are provided to inhibit apparent amplitude modulation in non-linear processing that causes distortion in a processed signal. One aspect of the invention includes a hearing aid. The hearing aid includes a microphone to receive an input signal, a speaker to reproduce the input signal, and a processor. The processor processes the input signal using a gain. The processor includes an inhibitor, which inhibits distortions, and an adjuster, which adjusts the gain. The inhibitor acts to smooth an envelope of the input signal to inhibit undesired modulation. The adjuster adjusts the gain if the envelope is either above or below a threshold.

Claims

1. A system, comprising:

a delay element configured to delay an input signal to produce a delayed signal;

a first filter configured to filter the delayed signal to produce a first filtered signal;

a second filter configured to filter the input signal to produce a second filtered signal;

an adder configured to combine the first and second filtered signals to produce a smooth envelope;

a comparator configured to calculate a difference between the smooth envelope and a threshold; and

an adjuster configured to adjust a gain based on whether the difference is greater than or less than zero.

2. The system of claim 1, further comprising a third filter configured to filter out frequencies from the input signal, wherein the frequencies are less than about 100 Hertz.

3. The system of claim 2, further comprising:

a first multiplier configured to;

receive the first filtered signal; and

square the first filtered signal to form a first squared signal;

a second multiplier configured to;

receive the second filtered signal; and

square the second filtered signal to form a second squared signal;

the adder further configured to combine the first and second filtered signals to form the smooth envelope by adding the first squared signal and the second squared signal; and

a limiter configured to;

receive the smooth envelope; and

limit the smooth envelope to a desired operating range.

4. The system of claim 1, wherein the adjuster is further configured to:

receive the difference, a release time constant, and an attack time constant.

5. The system claim 4, wherein:

the adjuster is further configured to receive a previous gain;

if the difference is negative, the adjuster increases the gain by right shifting bits of the previous gain by the release time constant to form a new gain and performs an additive inverse of the new gain; and

if the difference is positive, the adjuster decreases the gain by right shifting bits of the difference by the attack time constant to form the new gain.

6. The system of claim 5, further comprising:

a width adjuster configured to adjust a word width of the previous gain and produce an adjusted previous gain;

a second adder configured to add the new gain and the adjusted previous gain to produce the gain;

a limiter configured to limit the range of the gain so that the gain is positive;

a buffer configured to store the gain as a stored gain, wherein the stored gain is defined as the previous gain, which is presented to the adjuster and the width adjuster; and

a rounding circuit configured to round the stored gain to a smaller precision value to be compatible with an input width of subsequent circuitry that includes a digital-to-analog converter.

7. The system of claim 1, wherein the adjuster is further configured to:

receive the difference, a release time constant, and an attack time constant;

increase the gain if the difference is negative; and

decrease the gain if the difference is positive.

8. The system of claim 7, wherein:

the first filter includes a first digital delay that receives the input signal and produces a delayed digital signal;

the first filter includes a second comparator that determines a second difference between the input signal and the delayed digital signal;

the first filter includes a first multiplier that multiplies the second difference and a scale to form a scaled signal, wherein the scaled signal inhibits the first filter from overflow.

9. The system of claim 8, wherein:

the first filter includes a second adder that adds the scaled signal and a blocked signal to form a filtered signal;

the first filter includes a second digital delay that receives the filtered signal and presents a filtered signal that is delayed; and

the first filter includes a second multiplier that multiplies the filtered signal that is delayed and an alpha signal to form the blocked signal, wherein the alpha signal determines a range of frequencies that will be blocked by the first filter.

10. A digital analog gain control, comprising:

a delay element configured to delay an input signal to produce a delayed signal;

a first infinite-impulse-response (IIR) filter configured to produce a first filtered signal from the delayed signal;

a second IIR filter configured to produce a second filtered signal from the input signal;

an adder configured to combine the first and second filtered signals to produce a smooth envelope;

a comparator configured to calculate a difference between the smooth envelope and a threshold; and

an adjuster configured to;

receive the difference, a release time constant, and an attack time constant;

adjust a gain based at least in part on the difference being one of two conditions, wherein the two conditions include being a negative number and being a positive number,

increase the gain if the difference is negative; and

decrease the gain if the difference is positive.

11. The digital analog gain control of claim 10, wherein the first IIR filter includes a first delay, a second delay, and a scale element, wherein the input signal is delayed by the first delay, the is delayed by the second delay, and the input signal is scaled by the scale element to form a scaled signal.

12. The digital analog gain control of claim 11, wherein:

the first infinite-impulse response filter includes a second comparator that determines a second difference between the input signal and a feedback signal;

the first infinite-impulse-response filter includes a multiplier that multiplies the second difference and a beta signal to form a modified signal, wherein the beta signal modifies a phase of the difference;

the first infinite-impulse-response filter includes a third delay that delays modified signal to form a filtered signal; and

the first infinite-impulse-response filter includes a fourth delay that delays the filtered signal to form the feedback signal.

13. A method for controlling a gain of an amplifier, comprising:

delaying an input signal to produce a delayed signal,

filtering the delayed signal to produce a first filtered signal;

filtering the input signal to produce a second filtered signal;

combining the first and second filtered signals to produce a smooth envelope; and

subtracting the smooth envelope from a threshold to form a difference, wherein the difference is used to control the gain.

14. The method of claim 13, further comprising:

determining if the difference is greater than zero;

right shifting the bits of the difference by an attack constant to form a decreased gain; and

right shifting bits of a negated signal by a release constant to form an increased gain.

15. The method of claim 14, further comprising:

presenting the decreased gain as the gain if the difference is greater than zero; and

presenting the increased gain as the gain if the difference is less than zero.

16. The method of claim 15, further comprising:

summing the gain and a feedback signal that is delayed to form a modified gain signal;

presenting a final gain to an analog-to-digital converter, wherein the final gain is zero if the modified gain signal is less than or equal to zero, and the final gain is one if the modified gain signal is greater than one;

delaying the final gain to produce the feedback signal that is delayed; and

negating the feedback signal that is delayed to form the negated signal.

17. The method of claim 13, further comprising blocking low frequencies from the input signal.

18. The method of claim 17, where-in blocking includes blocking low frequencies that are less than about 100 Hertz.