Dynamic energy-saving method and apparatus for PCIE device, and communication system thereof

• US 9,563,257 B2
• Filed: 09/03/2013
• Issued: 02/07/2017
• Est. Priority Date: 04/18/2012
• Status: Active Grant

• Current Assignee: Huawei Technologies Co., Ltd. (Huawei Investment & Holding Co., Ltd.)
• Original Assignee: Huawei Technologies Co., Ltd. (Huawei Investment & Holding Co., Ltd.)
• Inventors: Fang, Qingyin, Qiu, Chaoping, Xia, Qiangzhi
• Primary Examiner(s): Nguyen, Phil
• Application Number:
  US14/016,786
• Publication Number:
  US 20140019788A1
• Time in Patent Office: 1,253 Days
• Field of Search: 713/323
• US Class Current: 1/1
• CPC Class Codes: G06F 1/325 Power saving in peripheral device
• CPC Class Codes: G06F 1/3253 Power saving in bus
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

The present disclosure is applicable to the field of device energy-saving control, and provides a dynamic energy-saving method and apparatus for a PCIE device, and a communication system thereof. The method includes: obtaining a system energy-saving policy; and using a PCIE energy-saving module to control a PCIE device and a PCIE link to enter a corresponding linkage energy-saving state according to the obtained system energy-saving policy. In the present disclosure, a “D” state of a PCIE device is associated with an “L” state of a link into a new linkage energy-saving state, and the device and the link are controlled to enter the corresponding linkage energy-saving state according to a preset energy-saving policy, thereby improving energy-saving efficiency.

Claims

1. An energy-saving method for a PCIE (Peripheral Component Interconnect-Express) device, the method comprising:

obtaining a system energy-saving policy; and

using a PCIE energy-saving module to control a PCIE device and a PCIE link to enter a corresponding linkage energy-saving state based on the obtained system energy-saving policy, wherein the linkage energy-saving state comprises P0, P0_L0s, P0_L1, P1, P2, or P3, wherein;

when the state is P0, the PCIE device is in a normal working state D0, and the PCIE link is in a fully active state L0,

when the state is P0_L0s, the PCIE device is in the normal working state D0, and the PCIE link is in a standby state L0s,

when the state is P0_L1, the PCIE device is in the normal working state D0, and the PCIE link is in a low-power-consumption standby state L1,

when the state is P1, the PCIE device is in a lowly dormant state D1, and the PCIE link is in the low-power-consumption standby state L1,

when the state is P2, the PCIE device is in a deep dormant state D2, and the PCIE link is in the low-power-consumption standby state L1, and

when the state is P3, the PCIE device is in a hot power-off state D3hot, and the PCIE link is in the low-power-consumption standby state L1 or a power-off stage L2/L3 ready;

wherein entering the P3 state comprises;

controlling, if the PCIE device supports the P1 state, the PICE device and the PCIE link to enter the P1 state and keep steady, and then controlling them to enter the P3 state,

controlling, if the PCIE device supports the P2 state, the PICE device and the PCIE link to enter the P2 state and keep steady, and then controlling them to enter the P3 state, and

controlling the PCIE device and the PCIE link to enter the P3 state directly if the PCIE device supports neither the P1 nor the P2 state.

2. The method according to claim 1, wherein before the step of obtaining a system energy-saving policy, the method further comprises:

initializing a PCIE energy-saving module.

3. The method according to claim 1, wherein the system energy-saving policy comprises:

non energy-saving state G0, lowly energy-saving state G1, moderately energy-saving state G2, or highly energy-saving state G3, wherein the G0 corresponds to the P0 state, the G1 corresponds to the P0_L0s state, the G2 corresponds to the P0_L1 state, and the G3 corresponds to the P3 state.

4. The method according to claim 3, wherein the step of using a PCIE energy-saving module to control a PCIE device and a PCIE link to enter a corresponding linkage energy-saving state based on the obtained system energy-saving policy comprises:

if the system energy-saving policy is the non energy-saving state G0, disabling energy-saving actions and controlling the PCIE device and the PCIE link to enter the P0 state;

if the system energy-saving policy is the lowly energy-saving state G1, recovering the P0 state for the PCIE device and the PCIE link that are not in the G1 state first, and then scanning an active state of each PCIE link, and controlling the PCIE link to enter the P0_L0s state if the PCIE link is in the active state;

if the system energy-saving policy is the moderately energy-saving state G2, recovering the P0 state for the PCIE device and the PCIE link that are not in the G2 state first, and then scanning an active state of each PCIE link, and controlling the PCIE link to enter the P0_L1 state if the PCIE link is in the active state; and

if the system energy-saving policy is the highly energy-saving state G3, recovering the P0 state for the PCIE device and the PCIE link that are not in the G3 state first, and then scanning an active state of each PCIE link, and controlling the PCIE link to enter the P3 state if the PCIE link is in an electrically idle state.

5. The method according to claim 4, wherein after the step of using a PCIE energy-saving module to control a PCIE device and a PCIE link to enter a corresponding linkage energy-saving state based on the obtained system energy-saving policy, the method further comprises:

controlling the PCIE device and the PCIE link to recover the P0 state upon detecting that any data on the PCIE link is accessed.

6. A dynamic energy-saving apparatus for a PCIE (Peripheral Component Interconnect-Express) device, comprising a processor and a computer-readable storage medium, the computer-readable storage medium having processor-executable instructions stored thereon, the processor-executable instructions including at least one module including:

a PCIE energy-saving module configured to control a PCIE device and a PCIE link to enter a corresponding linkage energy-saving state based on a system energy-saving policy, wherein the energy-saving state controlling module comprises;

a first controlling unit, configured to disable energy-saving actions and control the PCIE device and the PCIE link to enter a P0 state if the system energy-saving policy is a non energy-saving state G0,

a second controlling unit, configured to;

if the system energy-saving policy is a lowly energy-saving state G1, recover the P0 state for the PCIE device and the PCIE link that are not in the G1 state first, and then scan an active state of each PCIE link, and control the PCIE link to enter a P0_L0s state if the PCIE link is in the active state,

a third controlling unit, configured to;

if the system energy-saving policy is a moderately energy-saving state G2, recover the P0 state for the PCIE device and the PCIE link that are not in the G2 state first, and then scan the active state of each PCIE link, and control the PCIE link to enter a P0_L1 state if the PCIE link is in the active state, and

a fourth controlling unit, configured to;

if the system energy-saving policy is a highly energy-saving state G3, recover the P0 state for the PCIE device and the PCIE link that are not in the G3 state first, and then scan the active state of each PCIE link, and control the PCIE link to enter a P3 state if the PCIE link is in an electrically idle state;

wherein the system energy-saving policy comprises;

non energy-saving state G0, lowly energy-saving state G1, moderately energy-saving state G2, or highly energy-saving state G3, wherein the G0 corresponds to the P0 state, the G1 corresponds to the P0_L0s state, the G2 corresponds to the P0_L1 state, and the G3 corresponds to the P3 state;

wherein when the state is P0, the PCIE device is in a normal working state D0, and the PCIE link is in a fully active state L0;

wherein when the state is P0_L0s, the PCIE device is in a normal working state D0, and the PCIE link is in a standby state L0s;

wherein when the state is P0_L1, the PCIE device is in a normal working state D0, and the PCIE link is in a low-power-consumption standby state L1;

wherein when the state is P1, the PCIE device is in a lowly dormant state D1 and the PCIE link is in a low-power-consumption standby state L1;

wherein when the state is P2, the PCIE device is in a deep dormant state D2, and the PCIE link is in a low-power-consumption standby state L1; and

wherein when the state is P3, the PCIE device is in a hot power-off state D3hot, and the PCIE link is in a low-power-consumption standby state L1 or a power-off stage L2/L3 ready.

7. The apparatus according to claim 6, further comprising:

a device and PCIE link recovering unit, configured to, upon detecting that any data on a PCIE link is accessed, control the PCIE device and the PCIE link to recover a fully active state in which all energy-saving actions are disabled.