Array substrate and method of fabricating the same

• US 9,564,532 B2
• Filed: 11/15/2012
• Issued: 02/07/2017
• Est. Priority Date: 04/23/2012
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Display Co., Ltd.
• Inventors: Bae, Sang-Hyun, Kim, Ju-Yeon, Yoo, Yong-Woo
• Primary Examiner(s): Nguyen, Cuong Q
• Assistant Examiner(s): Yasmeen, Nishath
• Application Number:
  US13/678,369
• Publication Number:
  US 20130277668A1
• Time in Patent Office: 1,545 Days
• Field of Search: 257/40
• US Class Current: 1/1
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: H01L 21/44 Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/38 - H01L21/428
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1244 for preventing breakage, peeling or short circuiting
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H10K 59/1213 the pixel elements being TFTs

Abstract

An array substrate including a substrate including a pixel region; a gate line on the substrate; a gate electrode on the substrate and connected to the gate line; a gate insulating layer on the gate line and the gate electrode; a data line on the gate insulating layer and crossing the gate line to define the pixel region; a source electrode and a drain electrode on the gate insulating layer and corresponding to the gate electrode, the source electrode connected to the data line and the drain electrode spaced apart from the source electrode; and an oxide semiconductor layer on top of the source and drain electrodes.

Claims

1. An array substrate, comprising:

a substrate including a pixel region;

a gate line on the substrate;

a gate electrode on the substrate and connected to the gate line;

a gate insulating layer on the gate line and the gate electrode;

a data line on the gate insulating layer and crossing the gate line to define the pixel region;

a source electrode and a drain electrode on the gate insulating layer and corresponding to the gate electrode, the source electrode connected to the data line and the drain electrode spaced apart from the source electrode,

wherein a top layer of the source and drain electrodes includes copper or copper alloy and a bottom layer of the source and drain electrodes includes molybdenum or molybdenum-titanium alloy;

an adhesion enhancing layer formed on the top layer of the source and drain electrodes; and

an oxide semiconductor layer formed on the adhesion enhancing layer and the gate insulating layer disposed between the source and drain electrodes,

wherein the adhesion enhancing layer is a copper-nitride layer, directly contacts both the oxide semiconductor layer and the source and drain electrodes, and is positioned between the substrate and the oxide semiconductor layer.

2. The substrate according to claim 1, wherein a channel region between the source and drain electrodes does not include an etch stopper on top of the channel region.

3. The substrate according to claim 1, further comprising:

an additional adhesion layer on the data line.

4. The substrate according to claim 1, wherein the oxide semiconductor layer includes one of indium-gallium-zinc-oxide, zinc-tin-oxide and zinc-indium-oxide.

5. The substrate according to claim 1, further comprising:

a passivation layer on the oxide semiconductor layer and including a drain contact hole exposing the drain electrode; and

a pixel electrode on the passivation layer and in the pixel region, the pixel electrode contacting the drain electrode through the drain contact hole.

6. An oxide semiconductor thin film transistor, comprising:

a gate electrode formed on a substrate;

a gate insulating layer on the gate electrode;

source and drain electrodes on the gate insulating layer, wherein a top layer of the source and drain electrodes includes copper or copper alloy and a bottom layer of the source and drain electrodes includes molybdenum or molybdenum-titanium alloy;

an adhesion enhancing layer formed on the top layer of the source and drain electrodes; and

an oxide semiconductor layer formed on the adhesion enhancing layer and the gate insulating layer disposed between the source and drain electrodes,

wherein the adhesion enhancing layer is a copper-nitride layer, and electrically connects the oxide semiconductor layer to the source and drain electrodes, and

wherein the adhesion enhancing layer directly contacts both the oxide semiconductor layer and the source and drain electrodes, and is positioned between the substrate and the oxide semiconductor layer.

7. The oxide thin film transistor according to claim 6, wherein the gate electrode is a double layer and is of the same material as that of the source and drain electrodes.