Structure and method for testing stacked CMOS structure

• US 9,568,543 B2
• Filed: 10/25/2013
• Issued: 02/14/2017
• Est. Priority Date: 10/25/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Wang, Mill-Jer, Peng, Ching-Nen, Lin, Hung-Chih, Chen, Hao
• Primary Examiner(s): Hollington, Jermele M
• Assistant Examiner(s): YODICHKAS, KHRISTOPHER J
• Application Number:
  US14/062,935
• Publication Number:
  US 20150115993A1
• Time in Patent Office: 1,208 Days
• Field of Search: 324/762.03
• US Class Current: 1/1
• CPC Class Codes: G01R 31/2851 Testing of integrated circuits [IC] G01R31/317 takes precedence; testing individual devices G01R31/26; testing printed circuits G01R31/2801
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: G01R 31/318513 Test of Multi-Chip-Moduls
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout

Abstract

A test structure is provided for testing a semiconductor structure having a plurality of tiers. The test structure includes at least one conductive loop. Each respective conductive loop has ends defining at least one opening between the ends, and is embedded inside one or more of the plurality of tiers in the semiconductor structure. The test structure also includes at least two test pads on each respective conductive loop. The at least two test pads are connected with respective ends of each respective conductive loop. The test structure is configured to permit detection of defects within each of the plurality of tiers in the semiconductor structure if the defects exist, using a testing apparatus.

Claims

1. A test structure for testing a 3D semiconductor structure having a plurality of tiers, comprising

at least one conductive loop, each respective conductive loop comprising two pairs of ends in a top tier of the plurality of tiers and being embedded inside two or more of the plurality of tiers in the semiconductor structure, a first pair of ends and a second pair of ends being in a same loop and each defining one opening therebetween;

and

at least two test pads on each respective conductive loop, the at least two test pads electrically connected with respective ends of each respective conductive loop,

wherein

each respective conductive loop comprises at least one conductive ring in the two or more of the plurality of tiers; and

the respective conductive rings in at least two of the plurality of tiers are electrically connected with each other through inter-level vias across two adjacent tiers of the plurality of tiers and through the second pair of ends in the top tier to form the respective conductive loop.

2. The test structure of claim 1, wherein

the test structure is configured to permit detection of defects within each of the plurality of tiers in the semiconductor structure if the defects exist, using a testing apparatus.

3. The test structure of claim 1, wherein the at least one conductive loop is at least two conductive loops having substantially identical shape and length, and each respective loop has a different line width.

4. The test structure of claim 1, wherein

the at least one conductive loop is a first number of conductive loops having the same line width as each other;

and

each respective conductive loop is divided across a second number of tiers in the semiconductor structure, wherein the second number is different from the first number.

5. The test structure of claim 1, further comprising

a conductive mesh in a middle portion of the semiconductor structure, the conductive mesh routed through scribe lines within one respective tier of the semiconductor structure, and routed through inter-level vias connecting tiers in the semiconductor structure;

and

a plurality of additional test pads electrically connected with the conductive mesh on a surface tier of the semiconductor structure;

wherein the conductive mesh is configured to conduct a current between two of the plurality of additional test pads on the surface tier.

6. The test structure of claim 5, further comprising

at least one probe pad on the surface tier of the semiconductor structure;

a plurality of switches between two of the plurality of additional test pads on the surface tier, and

at least one multiplexer electrically connected to the at least one probe pad, the plurality of switches, and the plurality of additional test pads on the surface tier of the semiconductor structure;

wherein the at least one probe pad, a plurality of switches and the at least one multiplexer are configured to permit application of a voltage to a portion the conductive mesh between two of the additional test pads in the surface tier, to measure a corresponding current therethrough.

7. The test structure of claim 5, further comprising

a plurality of switches on the surface tier of the semiconductor structure, one of the switches electrically connected between two of the plurality of additional test pads on the surface tier,

wherein the plurality of additional test pads are configured to connect with an external probe card, and the external probe card is electrically connected to a portion the conductive mesh between two of the additional test pads in the surface tier, for measuring a corresponding current therethrough.

8. The test structure of claim 5, wherein

the conductive mesh has a tree structure and extends across the plurality of tiers in the semiconductor structure, wherein the tree structure comprises a respective scribe line within one respective tier branched into two conductive lines within an adjacent tier.

9. The test structure of claim 5, wherein

one of the inter-level vias comprises a pair of inter-level vias separated from each other by a predetermined distance.

10. A semiconductor structure having a plurality of tiers and comprising a test structure for testing the semiconductor structure, the test structure comprising

at least one conductive loop, each respective conductive loop comprising two pairs of ends in a top tier of the plurality of tiers and being embedded inside two or more of the plurality of tiers in the semiconductor structure, a first pair of ends and a second pair of ends being in a same loop and each defining one opening therebetween;

and

at least two test pads on each respective conductive loop, the at least two test pads electrically connected with respective ends of the at least one opening of each respective conductive loop,

wherein

each respective conductive loop comprises at least one conductive ring in the two or more of the plurality of tiers; and

the respective conductive rings in at least two if the plurality of tiers are electrically connected with each other through inter-level vias across two adjacent tiers of the plurality of tiers and through the second pair of ends in the top tier to form the respective conductive loop.

11. The semiconductor structure of claim 10, wherein

the test structure is configured to permit detection of defects within each of the plurality of tiers in the semiconductor structure if the defects exist, using a testing apparatus.

12. The semiconductor structure of claim 10, wherein the at least one conductive loop is at least two conductive loops having substantially identical shape and length, and each respective loop has a different line width.

13. The semiconductor structure of claim 10, wherein

the at least one conductive loop is a first number of conductive loops having the same line width as each other;

and

each respective conductive loop is divided across a second number of tiers in the semiconductor structure, wherein the second number is different from the first number.

14. The semiconductor structure of claim 10, wherein the test structure further comprises

a conductive mesh in a middle portion of the semiconductor structure, the conductive mesh routed through scribe lines within one respective tier of the semiconductor structure, and routed through inter-level vias connecting tiers in the semiconductor structure;

and

a plurality of additional test pads electrically connected with the conductive mesh on a surface tier of the semiconductor structure;

wherein the conductive mesh is configured to conduct a current between two of the plurality of additional test pads on the surface tier.

15. The semiconductor structure of claim 14, wherein the test structure further comprises

at least one probe pad on the surface tier of the semiconductor structure;

a plurality of switches between two of the plurality of additional test pads on the surface tier, and

at least one multiplexer electrically connected to the at least one probe pad, the plurality of switches, and the plurality of additional test pads on the surface tier of the semiconductor structure;

wherein the at least one probe pad, a plurality of switches and the at least one multiplexer are configured to permit application of a voltage to a portion the conductive mesh between two of the plurality of additional test pads in the surface tier, to measure a corresponding current therethrough.

16. The semiconductor structure of claim 14, wherein the test structure further comprises

a plurality of switches on the surface tier of the semiconductor structure, one of the switches electrically connected between two of the plurality of additional test pads on the surface tier,

wherein the plurality of additional test pads are configured to connect with an external probe card, and the external probe card is electrically connected to a portion the conductive mesh between two of the plurality of additional test pads in the surface tier, for measuring a corresponding current therethrough.

17. A semiconductor structure, comprising

a stacked complementary metal-oxide-semiconductor (CMOS) device having a plurality of tiers in a wafer, and

a test structure for testing the semiconductor structure, the test structure comprising

at least one conductive loop, each respective conductive loop comprising two pairs of ends in a top tier of the plurality of tiers and being embedded inside one or more of the plurality of tiers in the semiconductor structure, a first pair of ends and a second pair of ends being in the same of loop and each defining one opening therebetween;

at least two test pads on each respective conductive loop, the at least two test pads electrically connected with respective ends of the at least one opening of each respective conductive loop;

wherein;

each respective conductive loop comprises at least one conductive ring in the two or more of the plurality of tiers; and

the respective conductive rings of at least two of the plurality of tiers are electrically connected with each other through inter-level vias across two adjacent tiers of the plurality of tiers and through the second pair of ends in the top tier to form the respective conductive loop;

a conductive mesh in a middle portion of the semiconductor structure, the conductive mesh routed through scribe lines within one respective tier of the semiconductor structure, and routed through inter-level vias connecting tiers in the semiconductor structure; and

a plurality of additional test pads electrically connected with the conductive mesh on a surface tier of the semiconductor structure;

wherein the conductive mesh is configured to conduct a current between two of the plurality of test pads on the surface tier.

18. The semiconductor structure of claim 17, the conductive mesh has a tree structure and extends across the plurality of tiers in the semiconductor structure, wherein the tree structure comprises a respective scribe line within one respective tier branched into two conductive lines within an adjacent tier.