Digital voting logic for manufacturable finger asperity wafer-scale solid state palm print scan devices

• US 9,569,655 B2
• Filed: 04/25/2012
• Issued: 02/14/2017
• Est. Priority Date: 04/25/2012
• Status: Active Grant

• Current Assignee: Jack Harper
• Original Assignee: Jack Harper
• Inventors: Harper, Jack
• Primary Examiner(s): Rush, Eric
• Application Number:
  US13/455,477
• Publication Number:
  US 20130287271A1
• Time in Patent Office: 1,756 Days
• Field of Search: 382/115, 382/124, 382/125, 382/312, 396/15
• US Class Current: 1/1
• CPC Class Codes: G06F 18/2115 by evaluating different subsets according to an optimisation criterion, e.g. class separability, forward selection or backward elimination
• CPC Class Codes: G06K 7/08 by means detecting the change of an electrostatic or magnetic field, e.g. by detecting change of capacitance between electrodes
• CPC Class Codes: G06K 7/081 electrostatic, e.g. by detecting the charge of capacitance between electrodes
• CPC Class Codes: G06V 10/771 Feature selection, e.g. selecting representative features from a multi-dimensional feature space
• CPC Class Codes: G06V 40/12 Fingerprints or palmprints
• CPC Class Codes: G06V 40/1306 non-optical, e.g. ultrasonic or capacitive sensing
• CPC Class Codes: G06V 40/1347 Preprocessing; Feature extraction

Abstract

Techniques are disclosed herein for artificial intelligence machine learning to increase collection of digital livescan fingerprints. According to certain embodiments of the invention, processing parameters can be automatically machine-optimized for processing scan images of fingerprints (and other areas) to increase the amount of detected minutia. The processing parameters can alter and change over time to reflect historical successes and failures of particular optimizations. This allows a fingerprint collection device to learn over time and become more accurate (i.e., more successful at detecting minutia). Additionally, the techniques further include receiving input from a user regarding physical traits of a scanned subject, to further customize the processing parameter optimization. Various other features are provided herein.

Claims

1. An asperity scanning apparatus comprising:

a sensor module having a plurality of sensor cell clusters, wherein each sensor cell cluster includes;

a plurality of solid-state sensor cells, wherein each solid-state sensor cell is configured to;

make an measurement of asperity, and

provide a single-bit binary output based, at least in part, on the measurement of asperity; and

voting logic circuitry, comprising one or more two-input logical gates, coupled with each of the plurality of solid-state sensor cells and configured to provide a single binary output based on the single-bit binary output of each of the plurality of solid-state sensor cells;

wherein the sensor module of the asperity scanning apparatus is configured to output an image.

2. The asperity scanning apparatus as recited in claim 1, wherein a plurality of sensor cell clusters of the sensor module comprises a two-dimensional array of at least 1.75 inches by at least 5.5 inches in size.

3. The asperity scanning apparatus as recited in claim 1, wherein each of the plurality of sensor cell clusters comprises an odd number of solid-state sensor cells.

4. The asperity scanning apparatus as recited in claim 1, wherein the measurement of asperity of each of the plurality of solid-state sensor cells is based, at least in part, on a measurement of electrical resistance.

5. The asperity scanning apparatus as recited in claim 1 wherein the plurality of solid-state sensor cells for each of the plurality of sensor cell clusters comprises a group of adjacent solid-state sensor cells.

6. The asperity scanning apparatus as recited in claim 1, further comprising a device driver module configured to determine whether the sensor cell cluster is faulty.

7. The asperity scanning apparatus as recited in claim 6, wherein the device driver module is configured to determine whether the sensor cell cluster is faulty based, at least in part, on a calibration step that averages adjacent sensor cell clusters.

8. The asperity scanning apparatus as recited in claim 1, wherein the voting logic circuitry includes a combination of NAND gates and logical inverters.

9. A method for processing asperity data, the method comprising:

measuring asperity with each solid-state sensor cell of a plurality of solid-state sensor cells in a sensor cell cluster;

providing, with each solid-state sensor cell of the plurality of solid-state sensor cells, a single-bit binary output based, at least in part, on the measurement of asperity;

combining, using voting logic circuitry that comprises one or more two-input logical gates, the single-bit binary output of each of the plurality of solid-state sensor cells to provide a single binary output for the sensor cell cluster; and

creating an image of asperity features based, at least in part, on outputs of a plurality of sensor cell clusters.

10. The method for processing asperity data as recited in claim 9, wherein the single output for the sensor cell cluster is based on an odd number of single-bit binary outputs.

11. The method for processing asperity data as recited in claim 9, wherein measuring asperity with each solid-state sensor cell of the plurality of solid-state sensor cells is based, at least in part, on a measurement of electrical resistance.

12. The method for processing asperity data as recited in claim 9, further comprising determining whether the sensor cell cluster is faulty based, at least in part, on a calibration step that averages adjacent sensor cell clusters.

13. The method for processing asperity data as recited in claim 9, wherein combining the single-bit binary output of each of the plurality of solid-state sensor cells is performed by digital circuitry.

14. The method for processing asperity data as recited in claim 9, wherein the image of asperity features comprises at least a portion of a palm print.

15. The method for processing asperity data as recited in claim 9, wherein measuring asperity includes measuring a voltage drop.

16. A system for imaging friction ridges of skin, the system comprising:

sensing means for;

taking a measurement of asperity of a portion of the skin at each sensor cell of a plurality of sensor cells in a sensor cell cluster; and

providing a single-bit binary output for each sensor cell of the plurality of sensor cells, based, at least in part, on the measurement of asperity;

voting logic means for combining the single-bit binary output of each of the plurality of sensor cells to provide a single binary output for the sensor cell cluster, the voting logic means comprising one or more two-input logical gates; and

imaging means for creating an image of the friction ridges of the skin, at least in part, on outputs of a plurality of sensor cell clusters.

17. The system for imaging the friction ridges of the skin as recited in claim 16, wherein taking the measurement of asperity comprises measuring electrical resistance.

18. The system for imaging the friction ridges of the skin as recited in claim 16, further comprising calibration means for determining whether the sensor cell cluster is faulty based, at least in part, on a calibration step that averages adjacent sensor cell clusters.

19. The system for imaging the friction ridges of the skin as recited in claim 16, wherein the voting logic means includes digital logic circuitry.

20. The system for imaging the friction ridges of the skin as recited in claim 16, wherein the sensing means comprises a two-dimensional array of at least 1.75 inches by at least 5.5 inches in size.