Spacer passivation for high-aspect ratio opening film removal and cleaning

• US 9,570,460 B2
• Filed: 02/12/2015
• Issued: 02/14/2017
• Est. Priority Date: 07/29/2014
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: Kanakamedala, Senaka Krishna, Lee, Yao-Sheng, Makala, Raghuveer S., Matamis, George
• Primary Examiner(s): BACHNER, ROBERT G
• Application Number:
  US14/620,674
• Publication Number:
  US 20160035742A1
• Time in Patent Office: 733 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02063 the processing being the formation of vias or contact holes
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND

Abstract

A method of making a semiconductor device includes forming a stack of alternating layers of a first material and a second material over a substrate, etching the stack to form at least one opening in the stack such that a damaged region is located on a bottom surface of the at least one opening, forming a masking layer on a sidewall of the at least one opening while the bottom surface of the at least one opening is not covered by the masking layer, and further etching the bottom surface of the at least one opening remove the damaged region.

Claims

1. A method of making a semiconductor device, comprising:

forming a stack of alternating layers of a first material and a second material over a semiconductor material;

etching the stack to form at least one front side opening in the stack;

forming a memory film over a sidewall and bottom surface of the at least one front side opening;

forming a sacrificial cover layer over the memory film such that the sacrificial cover layer is deposited so that the sacrificial cover layer is formed over a sidewall portion of the memory film located over the sidewall of the at least one front side opening, but not over a bottom portion of the memory film located over the bottom of the at least one front side opening, wherein the sacrificial cover layer comprises carbon and the semiconductor material comprises a semiconductor substrate;

etching the bottom portion of the memory film at the bottom of the at least one front side opening to expose an upper surface of the semiconductor material while the sacrificial material layer protects the sidewall portion of the memory film during the etching step;

removing the sacrificial cover layer;

forming a semiconductor channel in the at least one front side opening;

etching a back side opening through the stack to the substrate;

removing the second material layers from the stack through the back side opening to form back side recesses between the first material layers in the stack;

forming control gate electrodes in the back side recesses through the back side opening;

forming a source region in the substrate through the back side opening;

forming an insulating layer on sidewalls of the back side opening such that a major surface of the substrate is exposed in the back side opening; and

forming a conductive source line in the back side opening over the insulating layer and in contact with the source region in the substrate;

wherein the method further comprises at least one of (a), (b) or (c);

(a) the memory film comprises a composite blocking dielectric comprising a high-k dielectric layer and a silicon oxide layer; and

/or

(b) forming a semiconductor cover layer between the memory film and the sacrificial cover layer and etching a bottom portion of the semiconductor cover layer at the bottom of the at least one front side opening to expose the upper surface of the semiconductor material while the sacrificial material layer protects a sidewall portion of the semiconductor channel during the etching step; and

/or

(c) etching the bottom portion of the memory film at the bottom of the at least one front side opening forms either a tapered opening or a reverse tapered opening.

2. The method of claim 1, wherein the carbon sacrificial cover layer is removed from the at least one front side opening by ashing.

3. The method of claim 1, further comprising depositing a dielectric material in a core of the at least one front side opening such that the semiconductor channel concentrically surrounds the dielectric material.

4. The method of claim 1, wherein the memory film comprises a charge trapping layer or floating gate and a tunnel dielectric, and the tunnel dielectric is located between the charge trapping layer or floating gate and the semiconductor channel.

5. The method of claim 4, wherein the memory film further comprises a blocking dielectric.

6. The method of claim 1, wherein:

the semiconductor device comprises a monolithic three dimensional NAND string in an array of monolithic three dimensional NAND strings located over a silicon substrate;

the monolithic three dimensional NAND string comprises at least one memory cell in the first device level located over another memory cell in the second device level of the three dimensional array of NAND strings; and

the silicon substrate contains an integrated circuit comprising a driver circuit for the memory device located thereon.

7. The method of claim 1, wherein the method further comprises (a) the memory film comprises the composite blocking dielectric comprising the high-k dielectric layer and the silicon oxide layer.

8. The method of claim 1, wherein the method further comprises (b) forming the semiconductor cover layer between the memory film and the sacrificial cover layer and etching the bottom portion of the semiconductor cover layer at the bottom of the at least one front side opening to expose the upper surface of the semiconductor material while the sacrificial material layer protects a sidewall portion of the semiconductor channel during the etching step.

9. The method of claim 1, wherein the method further comprises (c) etching the bottom portion of the memory film at the bottom of the at least one front side opening forms either the tapered opening or the reverse tapered opening.

10. A method of making a semiconductor device, comprising:

forming a stack of alternating layers of a first material and a second material over a semiconductor material;

etching the stack to form at least one front side opening in the stack, the at least one front side opening comprising a top opening defined by a top surface of the stack, a bottom surface opposite the top surface, and a sidewall defined at least in part by the alternating layers of the stack and extending between the top opening and the bottom surface;

forming a memory film over the sidewall and bottom surface of the at least one front side opening;

forming a sacrificial cover layer over the stack such that the sacrificial cover layer is deposited so that it forms a first portion over the top surface of the stack and at least partially covering the top opening of the at least one front side opening and a second portion over a sidewall portion of the memory film located over the sidewall of the at least one front side opening, wherein the first portion has a thickness that is greater than the thickness of the second portion;

etching the bottom portion of the memory film at the bottom of the at least one front side opening to expose an upper surface of a semiconductor material while the sacrificial cover layer protects the sidewall portion of the memory film during the etching step;

removing the sacrificial cover layer; and

forming a semiconductor channel in the at least one front side opening.

11. The method of claim 10, wherein the sacrificial cover layer is deposited so that it forms a third portion over the bottom surface of the at least one front side opening, and the third portion of the sacrificial cover layer is etched with the bottom portion of the memory film to expose the upper surface of the semiconductor material while the second portion of the sacrificial cover layer remain over the sidewall portion of the memory film.

12. The method of claim 11, wherein a thickness of the third portion is less than the thicknesses of the first and second portions.

13. The method of claim 10, wherein the second portion has a thickness that varies by less than 120% between a first end proximate to the top opening and a second end proximate to the bottom surface of the at least one memory opening.

14. The method of claim 10, wherein the thickness of the first portion is more than 225% of a maximum thickness of the second portion.

15. The method of claim 10, wherein:

the first portion of the sacrificial cover layer extends radially inward from the first end of the second portion of the sacrificial cover layer to at least partially cover the top opening of the at least one front side opening; and

the second portion has a thickness that is substantially constant or gradually tapers between a first end proximate to the top opening and a second end proximate to the bottom surface of the at least one memory opening.

16. The method of claim 10, wherein the method further comprises at least one of (a), (b) or (c):

(a) the memory film comprises a composite blocking dielectric comprising a high-k dielectric layer and a silicon oxide layer; and

/or

(b) forming a semiconductor cover layer between the memory film and the sacrificial cover layer and etching a bottom portion of the semiconductor cover layer at the bottom of the at least one front side opening to expose the upper surface of the semiconductor material while the sacrificial cover layer protects a sidewall portion of the semiconductor channel during the etching step; and

/or

(c) etching the bottom portion of the memory film at the bottom of the at least one front side opening forms either a tapered opening or a reverse tapered opening.

17. The method of claim 10, wherein the sacrificial cover layer comprises carbon and the semiconductor material comprises a semiconductor substrate, and the carbon sacrificial cover layer is removed from the at least one front side opening by ashing.

18. The method of claim 17, wherein the memory film comprises a charge trapping layer or floating gate and a tunnel dielectric, and the tunnel dielectric is located between the charge trapping layer or floating gate and the semiconductor channel.

19. The method of claim 18, wherein:

the memory film further comprises a blocking dielectric; and

a dielectric material is located in a core of the at least one front side opening such that the semiconductor channel concentrically surrounds the dielectric material.

20. The method of claim 17, further comprising:

etching a back side opening through the stack to the substrate;

removing the second material layers from the stack through the back side opening to form back side recesses between the first material layers in the stack;

forming control gate electrodes in the back side recesses through the back side opening;

forming a source region in the substrate through the back side opening;

forming an insulating layer on sidewalls of the back side opening such that a major surface of the substrate is exposed in the back side opening; and

forming a conductive source line in the back side opening over the insulating layer and in contact with the source region in the substrate.

21. The method of claim 10, wherein:

the semiconductor device comprises a monolithic three dimensional NAND string in an array of monolithic three dimensional NAND strings located over a silicon substrate;

the monolithic three dimensional NAND string comprises at least one memory cell in the first device level located over another memory cell in the second device level of the three dimensional array of NAND strings; and

the silicon substrate contains an integrated circuit comprising a driver circuit for the memory device located thereon.