Semiconductor device having stressor and method of forming the same

• US 9,577,097 B2
• Filed: 07/23/2015
• Issued: 02/21/2017
• Est. Priority Date: 12/08/2014
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Jaehoon
• Primary Examiner(s): YUSHINA, GALINA G
• Application Number:
  US14/806,782
• Publication Number:
  US 20160163860A1
• Time in Patent Office: 579 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/267 in different semiconductor regions , e.g. heterojunctions H01L29/263 takes precedence
• CPC Class Codes: H01L 29/41783 Raised source or drain electrodes self aligned with the gate
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/7378 comprising lattice mismatched active layers, e.g. SiGe strained layer transistors
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

A semiconductor device having a stressor is provided. A first trench and a second trench spaced apart from each other are formed in a substrate. A channel area is defined between the first trench and the second trench. A gate dielectric layer is formed on the channel area. A gate electrode is formed on the gate dielectric layer. The stressor includes a plurality of semiconductor layers formed in the first trench and the second trench and a plurality of interlayers formed between the semiconductor layers. Sidewalls of the first trench and the second trench are v-shaped (e.g., have a < or > shape).

Claims

1. A semiconductor device, comprising:

a substrate comprising a first trench and a second trench, wherein the trenches are spaced apart from each other, and a channel area is defined between the trenches;

a gate dielectric layer disposed on the channel area;

a gate electrode disposed on the gate dielectric layer; and

a stressor including a plurality of semiconductor layers formed in the first trench and the second trench and a plurality of interlayers formed between the semiconductor layers,

wherein the interlayers have a different bandgap than that of the semiconductor layers,

wherein a lowermost one of the semiconductor layers is undoped with impurity, and

wherein the other semiconductor layers on the lowermost one of the semiconductor layers are doped with impurity.

2. The semiconductor device of claim 1, wherein a content of Ge in each of the other semiconductor layers is higher than that in the lowermost one of the semiconductor layers.

3. The semiconductor device of claim 1, further comprising:

a capping layer disposed on the stressor;

a first spacer disposed on a side surface of the gate dielectric layer; and

a second spacer contacting the first spacer and disposed on an upper surface of the capping layer covering the stressor.

4. The semiconductor device of claim 1, wherein the gate dielectric layer is in contact with a bottom or a sidewall of the gate electrode, and an upper end of the gate dielectric layer is formed at a higher level than a center of the gate electrode.

5. The semiconductor device of claim 1, wherein the interlayers include a pseudomorphic monolayer, a pseudomorphic multilayer, or a combination thereof.

6. The semiconductor device of claim 1, wherein the interlayers include SoN, SiO, CN, SiCN, GaN, AlN, InN, GaAs, SiC, Ge, Si, a Si/Ge superlattice, or a combination thereof.

7. The semiconductor device of claim 1,

wherein the semiconductor layers comprise first, second, and third semiconductor layers,

wherein the interlayers comprises first and second interlayers,

wherein, for each of the first trench and the second trench, the first semiconductor layer is in contact with sidewalls of the trench,

wherein the first interlayer is disposed on the first semiconductor layer,

wherein the second semiconductor layer is disposed on the first interlayer,

wherein the second interlayer is disposed on the second semiconductor layer, and

wherein the third semiconductor layer is disposed on the second interlayer.

8. The semiconductor device of claim 7, wherein sidewalls of the first semiconductor layer and the first interlayer are v-shaped.

9. The semiconductor device of claim 7, wherein the first interlayer is thinner than the first semiconductor layer.

10. The semiconductor device of claim 7, wherein the first interlayer has a thickness in a range from 0.1 am to 10 nm.

11. The semiconductor device of claim 7, wherein the second semiconductor layer is thicker than the first semiconductor layer.

12. A semiconductor device, comprising:

a substrate comprising a first trench and a second trench, wherein the trenches are spaced apart from each other, and a channel area is defined between the trenches;

a gate dielectric layer disposed on the channel area;

a gate electrode disposed on the gate dielectric layer; and

a stressor including a plurality of semiconductor layers formed in the first trench and the second trench and a plurality of interlayers formed between the semiconductor layers,

wherein a lowermost one of the semiconductor layers is undoped with impurity, and

wherein the other semiconductor layers on the lowermost one of the semiconductor layers are doped with impurity.

13. The semiconductor device of claim 12, further comprising:

a capping layer disposed on the stressor;

a first spacer disposed on a side surface of the gate dielectric layer; and

a second spacer contacting the first spacer and disposed on an upper surface of the capping layer covering the stressor.

14. The semiconductor device of claim 12, wherein the gate dielectric layer is in contact with a bottom or a sidewall of the gate electrode, and an upper end of the gate dielectric layer is formed at a higher level than a center of the gate electrode.

15. The semiconductor device of claim 12, wherein the interlayers include a pseudomorphic monolayer, a pseudomorphic multilayer, or a combination thereof.

16. The semiconductor device of claim 12, wherein the interlayers include SoN, SiO, CN, SiCN, GaN, AlN, InN, GaAs, SiC, Ge, Si, a Si/Ge superlattice, or a combination thereof.

17. The semiconductor device of claim 12,

wherein the semiconductor layers comprise first, second, and third semiconductor layers,

wherein the interlayers comprises first and second interlayers,

wherein, for each of the first trench and the second trench, the first semiconductor layer is in contact with sidewalls of the trench,

wherein the first interlayer is disposed on the first semiconductor layer,

wherein the second semiconductor layer is disposed on the first interlayer,

wherein the second interlayer is disposed on the second semiconductor layer, and

wherein the third semiconductor layer is disposed on the second interlayer.

18. The semiconductor device of claim 17, wherein sidewalls of the first semiconductor layer and the first interlayer are v-shaped.

19. The semiconductor device of claim 17, wherein the first interlayer is thinner than the first semiconductor layer.

20. The semiconductor device of claim 17, wherein the first interlayer has a thickness in a range from 0.1 nm to 10 nm.

21. The semiconductor device of claim 17, wherein the second semiconductor layer is thicker than the first semiconductor layer.