Semiconductor device with isolating layer on side and bottom surfaces

• US 9,583,565 B2
• Filed: 06/05/2015
• Issued: 02/28/2017
• Est. Priority Date: 06/05/2014
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Poelzl, Martin
• Primary Examiner(s): Page, Dale E
• Assistant Examiner(s): BODNAR, JOHN A
• Application Number:
  US14/731,970
• Publication Number:
  US 20150357408A1
• Time in Patent Office: 634 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02233 of the semiconductor substrate or a semiconductor layer
• CPC Class Codes: H01L 21/31051 Planarisation of the insulating layers H01L21/31058 takes precedence
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/762 Dielectric regions , e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
• CPC Class Codes: H01L 21/76264 SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0684 characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
• CPC Class Codes: H01L 29/0692 Surface layout

Abstract

A method for manufacturing a semiconductor device comprises includes providing a substrate with a surface, forming an isolating layer on part of the surface, and forming a first semiconductor portion and spaced therefrom a second semiconductor portion on the surface of the substrate. The isolating layer is interposed between a side surface of the first semiconductor portion and a side surface of the second semiconductor portion which face each other. The method further includes forming a first side isolation layer on the side surface of the first semiconductor portion.

Claims

1. A method for manufacturing a semiconductor device comprising:

providing a substrate with a surface;

forming an isolating layer on part of the surface;

forming a first semiconductor portion and forming a second semiconductor portion spaced therefrom with a portion directly on the surface of the substrate,

wherein the isolating layer is interposed between a side surface of the first semiconductor portion and a side surface of the second semiconductor portion, which face each other,

wherein the isolating layer comprises a first intermediate portion that is covered by the first semiconductor portion;

and forming a first side isolation layer on the side surface of the first semiconductor portion,

and removing an exposed portion of the isolating layer so that the first intermediate portion and the first side portion form a first L-shaped isolation.

2. The method of claim 1, further comprising:

forming a second side isolation layer on the side surface of the second semiconductor portion.

3. The method of claim 1, wherein the isolating layer further comprises a second intermediate portion and a part of the second semiconductor portion covers the second intermediate portion.

4. The method of claim 1, further comprising forming a first top isolation layer on a surface of the first semiconductor portion opposite to the substrate, and forming a second top isolation layer on a surface of the second semiconductor portion opposite to the substrate.

5. The method of claim 4, wherein the act of forming the first top isolation layer and the second top isolation layer and the act of forming the first side isolation layer and the second side isolation layer are performed by an oxidation process comprising oxidizing exposed surfaces of the first semiconductor portion and the second semiconductor portion.

6. The method of claim 4, further comprising:

forming a first masking layer on the first top isolation layer opposite the substrate and forming a second masking layer on the second top isolation layer opposite to the substrate,

wherein the first masking layer is formed on part of first top isolation layer so that a first portion of the first top isolation layer remains exposed, and the second masking layer is formed on part of the second top isolation layer so that a second portion of the second top isolation layer remains exposed.

7. The method of claim 6, wherein the exposed portion of the isolating layer is removed such that the second intermediate portion and the second side portion form a second L-shaped isolation.

8. The method of claim 6, further comprising:

removing the first top isolation layer and the second top isolation layer or removing the first masking layer and the second masking layer.

9. The method according of claim 4, further comprising:

forming at least one of the following structures between the first and second semiconductor portions;

forming a protrusion of the substrate; and

forming a protrusion of the substrate and a third top isolating layer on the protrusion.

10. A method for manufacturing a semiconductor device comprising:

providing a substrate with a surface;

forming an isolating layer on part of the surface;

forming a first semiconductor portion and forming a second semiconductor portion spaced therefrom with a portion directly on the surface of the substrate, wherein the isolating layer is interposed between a side surface of the first semiconductor portion and a side surface of the second semiconductor portion, which face each other;

and forming a first side isolation layer on the side surface of the first semiconductor portion, wherein the isolating layer comprises a first intermediate portion and a second intermediate portion and a part of the first semiconductor portion covers the first intermediate portion and a part of the second semiconductor portion covers the second intermediate portion.