Load-store dependency predictor PC hashing
First Claim
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1. An apparatus comprising:
- a plurality of entries, each of said entries being configured to store an identifier; and
circuitry comprising a first hashing stage and a second hashing stage, wherein the circuitry is configured to;
hash in the first hashing stage a portion of a program counter (PC) value of a given operation with at least a portion of a corresponding architectural register number or a micro-op number to produce an intermediate result, wherein the circuitry is configurable to switch between using the corresponding architectural register number or the micro-op number to produce the intermediate result; and
hash in the second hashing stage at least a portion of the intermediate result with a portion of the PC value of the given operation, the corresponding architectural register number, and the micro-op number to produce a first identifier;
store the first identifier in an entry of the plurality of entries; and
predict a first operation is dependent on a second operation based at least in part on the first operation having a second identifier that matches the first identifier stored in said entry of the plurality of entries.
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Abstract
Methods and processors for managing load-store dependencies in an out-of-order instruction pipeline. A load store dependency predictor includes a table for storing entries for load-store pairs that have been found to be dependent and execute out of order. Each entry in the table includes hashed values to identify load and store operations. When a load or store operation is detected, the PC and an architectural register number are used to create a hashed value that can be used to uniquely identify the operation. Then, the load store dependency predictor table is searched for any matching entries with the same hashed value.
93 Citations
15 Claims
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1. An apparatus comprising:
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a plurality of entries, each of said entries being configured to store an identifier; and circuitry comprising a first hashing stage and a second hashing stage, wherein the circuitry is configured to; hash in the first hashing stage a portion of a program counter (PC) value of a given operation with at least a portion of a corresponding architectural register number or a micro-op number to produce an intermediate result, wherein the circuitry is configurable to switch between using the corresponding architectural register number or the micro-op number to produce the intermediate result; and hash in the second hashing stage at least a portion of the intermediate result with a portion of the PC value of the given operation, the corresponding architectural register number, and the micro-op number to produce a first identifier; store the first identifier in an entry of the plurality of entries; and predict a first operation is dependent on a second operation based at least in part on the first operation having a second identifier that matches the first identifier stored in said entry of the plurality of entries. - View Dependent Claims (2, 3, 4, 5)
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6. A processor comprising:
circuitry comprising a first hashing stage and a second hashing stage, wherein the circuitry is configured to; hash in the first hashing stage a portion of a program counter (PC) value of a given operation with at least a portion of a corresponding architectural register number or a micro-op number to produce an intermediate result, wherein the circuitry is configurable to switch between using the corresponding architectural register number or the micro-op number to produce the intermediate result; and hash in the second hashing stage at least a portion of the intermediate result with a portion of the PC value of the given operation, the corresponding architectural register number, and the micro-op number to produce a first identifier; and store the first identifier in an entry of a plurality of entries; a load-store dependency predictor comprising said plurality of entries, each of said entries being configured to store an identifier generated by the circuitry; and circuitry configured to; predict a first operation is dependent on a second operation based at least in part on the first operation having a second identifier that matches the first identifier stored in said entry of the plurality of entries. - View Dependent Claims (7, 8, 9, 10)
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11. A method comprising:
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generating a first identifier, wherein the first identifier is generated by circuitry comprising a plurality of hashing stages, wherein a first hashing stage of the plurality of hashing stages is configured to hash a first portion of a program counter (PC) value of a given operation with at least a portion of a corresponding architectural register number or a micro-op number to produce an intermediate result, wherein the first hashing stage is configurable to switch between using the corresponding architectural register number or the micro-op number to produce the intermediate result, and wherein a second hashing stage of the plurality of hashing stages is configured to hash at least a portion of the intermediate result with a portion of the PC value of the given operation, the corresponding architectural register number, and the micro-op number to produce the first identifier; storing the first identifier by the circuitry in an entry of a plurality of entries of a load-store dependency predictor; and predicting by circuitry a first operation is dependent on a second operation based at least in part on the first operation having a second identifier that matches the first identifier stored in said entry of the plurality of entries. - View Dependent Claims (12, 13, 14, 15)
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Specification