Transistors incorporating metal quantum dots into doped source and drain regions

• US 9,601,630 B2
• Filed: 06/28/2013
• Issued: 03/21/2017
• Est. Priority Date: 09/25/2012
• Status: Active Grant

• Current Assignee: STMicroelectronics International N.V. (STMicroelectronics NV)
• Original Assignee: STMicroelectronics Incorporated (STMicroelectronics NV)
• Inventors: Zhang, John H.
• Primary Examiner(s): HALL, VICTORIA KATHLEEN
• Application Number:
  US13/931,096
• Publication Number:
  US 20140084245A1
• Time in Patent Office: 1,362 Days
• Field of Search: 257/20, 438/270
• US Class Current: 1/1
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/127 Quantum box structures
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/413 Nanosized electrodes, e.g. nanowire electrodes comprising one or a plurality of nanowires nanosized carbon materials, e.g. carbon nanotubes, per se C01B32/15; transparent electrodes comprising carbon nano-tubes H10K30/821, nanotechnology per se B82B
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/41775 characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
• CPC Class Codes: H01L 29/41783 Raised source or drain electrodes self aligned with the gate
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/4975 being a silicide layer, e.g. TiSi2
• CPC Class Codes: H01L 29/66431 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT with an active layer made of a group 13/15 material H01L29/66462
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/775 : with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/7781 : with inverted single heterostructure, i.e. with active layer formed on top of wide bandgap layer, e.g. IHEMT
• CPC Class Codes: H01L 29/78618 : characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78696 : characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

Metal quantum dots are incorporated into doped source and drain regions of a MOSFET array to assist in controlling transistor performance by altering the energy gap of the semiconductor crystal. In a first example, the quantum dots are incorporated into ion-doped source and drain regions. In a second example, the quantum dots are incorporated into epitaxially doped source and drain regions.

Claims

1. A transistor, comprising:

a substrate;

an isolation region formed in the substrate;

a fully recessed metal gate formed in the substrate within the isolation region, the fully recessed metal gate including a gate dielectric and a metal gate electrode;

a metal source region being a first carrier reservoir on a first side of the fully recessed metal gate, the metal source region having a contact including a first metal quantum dot;

a metal drain region being a second carrier reservoir on a second side of the fully recessed metal gate, the second side opposite the first side, the metal drain region having a contact including a second metal quantum dot; and

a channel region in contact with the fully recessed metal gate and extending between the first and second carrier reservoirs.

2. The transistor of claim 1, wherein when the transistor is an NFET, the first and second carrier reservoirs include silicon regions doped with phosphorous or silicon phosphide, and when the transistor is a PFET, the first and second carrier reservoirs include silicon regions doped with boron or boron silicon germanium.

3. The transistor of claim 1 wherein, when the transistor is a PFET, the first and second carrier reservoirs are lined with platinum silicide, and when the transistor is an NFET, the first and second carrier reservoirs are lined with nickel silicide, the silicide thicknesses ranging from 1-20 nm.

4. The transistor of claim 1 wherein, when the transistor is a PFET, the first and second carrier reservoirs are lined with platinum silicide, and when the transistor is an NFET, the first and second carrier reservoirs are lined with a rare earth metal silicide, the silicide thicknesses ranging from 1-20 nm.

5. The transistor of claim 4 wherein the rare earth metal silicide includes one or more of yttrium silicide or erbium silicide.

6. The transistor of claim 1 wherein the metal gate electrode is made of tungsten and includes a liner of thickness 1-10 nm made of titanium or titanium nitride.

7. The transistor of claim 1 wherein the metal gate electrode is made of copper and includes a liner of thickness 1-10 nm made of tantalum nitride.

8. The transistor of claim 1 wherein the gate dielectric has a high dielectric constant greater than about 4.0.

9. The transistor of claim 1 wherein the channel region is epitaxial.

10. The transistor of claim 9 wherein the channel region is in contact with at least three sides of the fully recessed metal gate.

11. A transistor array layout, comprising:

a plurality of transistors having source and drain regions, the source and drain regions being doped silicon carrier reservoirs;

a first regular surface pattern of metal quantum dots having planar surfaces, the metal quantum dots embedded within the source and drain regions such that all sidewall surfaces of the metal quantum dots are enclosed by the respective doped silicon carrier reservoir; and

a second regular surface pattern of gate array elements disposed between adjacent ones of the metal quantum dots.

12. The transistor array layout of claim 11 wherein the first and second regular surface patterns have different shapes.

13. The transistor array layout of claim 11 wherein shapes of the metal quantum dots, as seen from a top plan view, include one or more of circles, ellipses, or polygons.

14. The transistor array layout of claim 11 wherein the metal quantum dots are arranged in a periodic lattice structure.

15. A transistor comprising:

a substrate;

an isolation region in the substrate;

a non-planar conducting channel formed in the substrate;

a source region formed in the substrate and in contact with the non-planar conducting channel, the source region including a first doped carrier reservoir that, in operation, injects charge into the non-planar conducting channel;

a drain region formed in the substrate and in contact with the non-planar conducting channel, the drain region including a second doped carrier reservoir that, in operation, injects charge into the non-planar conducting channel;

metal quantum dots embedded as contacts in the source and drain regions such that a top side of the metal quantum dots are coplanar with a top side of the source and drain regions, and all other sides of the metal quantum dots are enclosed by silicon; and

a fully recessed metal gate formed in the substrate.

16. The transistor of claim 15 wherein the non-planar conducting channel is made of an epitaxially grown material.

17. The transistor of claim 15 wherein the fully recessed metal gate contacts at least three sides of the non-planar conducting channel.

18. The transistor of claim 15 wherein the fully recessed metal gate includes a gate dielectric having a dielectric constant greater than about 4.0.

19. The transistor of claim 15 wherein the first and second doped carrier reservoirs each have a doping concentration within the range of about 1.0 E19-1.0 E21 atoms/cm³.

20. The transistor of claim 15 further comprising metal silicides adjacent to the metal quantum dots, the metal silicides incorporating dopants from the first and second doped carrier reservoirs.