Methods for sharing bandwidth across a packetized bus and systems thereof

• US 9,606,946 B2
• Filed: 10/29/2014
• Issued: 03/28/2017
• Est. Priority Date: 01/16/2009
• Status: Active Grant

• Current Assignee: F5 Networks, Inc. (F5 Incorporated)
• Original Assignee: F5 Networks, Inc. (F5 Incorporated)
• Inventors: Michels, Tim S.
• Primary Examiner(s): RECEK, JASON D
• Application Number:
  US14/527,388
• Publication Number:
  US 20150149681A1
• Time in Patent Office: 881 Days
• Field of Search: 709/225, 709/230, 709/246
• US Class Current: 1/1
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 13/287 Multiplexed DMA G06F13/30 takes precedence

Abstract

A system, method, and computer readable medium for sharing bandwidth among executing application programs across a packetized bus for packets from multiple DMA channels includes receiving at a network traffic management device first and second network packets from respective first and second DMA channels. The received packets are segmented into respective one or more constituent CPU bus packets. The segmented constituent CPU bus packets are interleaved for transmission across a packetized CPU bus.

Claims

1. A method for sharing bus bandwidth, the method comprising:

segmenting by a network traffic management device a first read request packet received from a first direct memory access (DMA) channel into one or more first constituent central processing unit (CPU) bus read request packets and a second read request packet received from a second DMA channel into one or more second constituent CPU bus read request packets;

accessing by the network traffic management device and from a memory coupled to a packetized CPU bus one or more first constituent CPU bus read completion packets corresponding to the one or more first constituent CPU bus read request packets and one or more second constituent CPU bus read completion packets corresponding to the one or more second constituent CPU bus read request packets; and

alternately transmitting by the network traffic management device the one or more first constituent CPU bus read completion packets of the first DMA channel and the one or more second constituent CPU bus read completion packets of the second DMA channel across a packetized CPU bus, wherein one or more of the first constituent CPU bus read completion packets comprises a same size as one or more of the second constituent CPU bus read completion packets.

2. The method as set forth in claim 1, further comprising reassembling by the network traffic management device the interleaved one or more first constituent CPU bus read completion packets into a first network packet and the interleaved one or more second constituent CPU bus read completion packets into a second network packet for transmission across a network link in response to the first and second read request packets.

3. The method of claim 1, wherein the first and second read request packets are in a transmission control protocol (TCP) format with a header and a payload.

4. The method as set forth in claim 1, wherein the one or more of the first constituent CPU bus read request packets, one or more of the second constituent CPU bus read request packets, one or more of the first constituent CPU bus read completion packets, or one or more of the second constituent CPU bus read completion packets are HyperTransport bus packets.

5. The method as set forth in claim 1, wherein the one or more of the first constituent CPU bus read request packets, one or more of the second constituent CPU bus read request packets, one or more of the first constituent CPU bus read completion packets, or one or more of the second constituent CPU bus read completion packets are PCI Express bus packets.

6. The method as set forth in claim 1, wherein the first and second read request packets are associated with first and second application programs that are each associated with a separate one of the first and second DMA channels.

7. A network traffic management device, comprising memory comprising programmed instructions stored in the memory and one or more processors configured to be capable of executing the programmed instructions stored in the memory to:

segment the a first read request packet received from a first direct memory access (DMA) channel into one or more first constituent central processing unit (CPU) bus read request packets and a second read request packet received from a second DMA channel into one or more second constituent CPU bus read request packets;

access and from a memory coupled to a packetized CPU bus one or more first constituent CPU bus read completion packets corresponding to the one or more first constituent CPU bus read request packets and one or more second constituent CPU bus read completion packets corresponding to the one or more second constituent CPU bus read request packets; and

alternately transmit the one or more first constituent CPU bus read completion packets of the first DMA channel and the one or more second constituent CPU bus read completion packets of the second DMA channel across a packetized CPU bus, wherein one or more of the first constituent CPU bus read completion packets comprises a same size as one or more of the second constituent CPU bus read completion packets.

8. The network traffic management device of claim 7, wherein the one or more processors are further configured to be capable of executing the programmed instructions stored in the memory to reassemble the interleaved one or more first constituent CPU bus read completion packets into a first network packet and the interleaved one or more second constituent CPU bus read completion packets into a second network packet for transmission across a network link in response to the first and second read request packets.

9. The network traffic management device of claim 7, wherein the first and second read request packets are in a transmission control protocol (TCP) format with a header and a payload.

10. The network traffic management device of claim 7, wherein the one or more of the first constituent CPU bus read request packets, one or more of the second constituent CPU bus read request packets, one or more of the first constituent CPU bus read completion packets, or one or more of the second constituent CPU bus read completion packets are HyperTransport bus packets.

11. The network traffic management device of claim 7, wherein the one or more of the first constituent CPU bus read request packets, one or more of the second constituent CPU bus read request packets, one or more of the first constituent CPU bus read completion packets, or one or more of the second constituent CPU bus read completion packets are PCI Express bus packets.

12. The network traffic management device of claim 7, wherein the first and second read request packets are associated with first and second application programs that are each associated with a separate one of the first and second DMA channels.

13. A non-transitory computer readable medium having stored thereon instructions for facilitating cipher selection comprising executable code which when executed by one or more processors, causes the processors to perform steps comprising:

segmenting the a first read request packet received from a first direct memory access (DMA) channel into one or more first constituent central processing unit (CPU) bus read request packets and a second read request packet received from a second DMA channel into one or more second constituent CPU bus read request packets;

accessing and from a memory coupled to a packetized CPU bus one or more first constituent CPU bus read completion packets corresponding to the one or more first constituent CPU bus read request packets and one or more second constituent CPU bus read completion packets corresponding to the one or more second constituent CPU bus read request packets; and

alternately transmitting the one or more first constituent CPU bus read completion packets of the first DMA channel and the one or more second constituent CPU bus read completion packets of the second DMA channel across a packetized CPU bus, wherein one or more of the first constituent CPU bus read completion packets comprises a same size as one or more of the second constituent CPU bus read completion packets.

14. The non-transitory computer readable medium of claim 13, wherein the executable code when executed by the processors causes the processor to perform one or more additional steps comprising reassembling the interleaved one or more first constituent CPU bus read completion packets into a first network packet and the interleaved one or more second constituent CPU bus read completion packets into a second network packet for transmission across a network link in response to the first and second read request packets.

15. The non-transitory computer readable medium of claim 13, wherein the first and second read request packets are in a transmission control protocol (TCP) format with a header and a payload.

16. The non-transitory computer readable medium of claim 13, wherein the one or more of the first constituent CPU bus read request packets, one or more of the second constituent CPU bus read request packets, one or more of the first constituent CPU bus read completion packets, or one or more of the second constituent CPU bus read completion packets are HyperTransport bus packets.

17. The non-transitory computer readable medium of claim 13, wherein the one or more of the first constituent CPU bus read request packets, one or more of the second constituent CPU bus read request packets, one or more of the first constituent CPU bus read completion packets, or one or more of the second constituent CPU bus read completion packets are PCI Express bus packets.

18. The non-transitory computer readable medium of claim 13, wherein the first and second read request packets are associated with first and second application programs that are each associated with a separate one of the first and second DMA channels.