Dynamically reconfigurable analog routing circuits and methods for system on a chip

• US 9,612,987 B2
• Filed: 05/07/2010
• Issued: 04/04/2017
• Est. Priority Date: 05/09/2009
• Status: Active Grant

• Current Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Sullam, Bert, Kutz, Harold, Williams, Timothy, Shutt, James, Byrkett, Bruce E., Richmond, Melany Ann, Kohagen, Nathan, Hastings, Mark, Thiagarajan, Eashwar, Snyder, Warren
• Primary Examiner(s): EBRAHIM, ANEZ C
• Application Number:
  US12/776,323
• Publication Number:
  US 20110026519A1
• Time in Patent Office: 2,524 Days
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 2213/0038 System on Chip

Abstract

An integrated circuit device may include a reconfigurable analog signal switching fabric comprising a plurality of global buses that are selectively connected to external pins by pin connection circuits in response to changeable analog routing data, and a plurality of local buses that are selectively connected to analog blocks and/or global buses by routing connection circuits in response to the analog routing data; and at least one processor circuit that executes predetermined operations in response to instruction data.

Claims

1. An integrated circuit device comprising:

a dynamically or statically reconfigurable analog signal switching fabric comprising;

a plurality of global buses configured to be selectively connected to and disconnected from external pins by pin connection circuits in response to first analog routing data; and

a plurality of local buses configured to be selectively connected to at least one of one or more analog blocks and one or more of the global buses by routing connection circuits in response to second analog routing data and in response to third analog data, to be selectively connected to a first of the one or more analog blocks and a second of the one or more analog blocks to connect the first and second analog blocks, wherein the first and second analog blocks are configured to provide an analog function, when connected to one another;

at least one processor circuit;

a programmable logic section comprising a plurality of digital programmable blocks; and

a digital system interconnect configured to provide, to the analog switching fabric, analog routing data received from the programmable logic section and analog routing data received from the at least one processor circuit.

2. The integrated circuit device of claim 1, wherein the pin connection circuits comprise switch circuits configured to selectively connect one external pin to any of the plurality of global buses in response to the analog routing data.

3. The integrated circuit device of claim 1, wherein the pin connection circuits comprise multiplexer circuits configured to selectively connect one external pin to any one of the plurality of global buses in response to the analog routing data.

4. The integrated circuit of claim 1, wherein the routing connection circuits comprise switch circuits configured to selectively connect at least one analog block to at least one of any of the local buses, and any of the global buses, in response to the analog routing data.

5. The integrated circuit of claim 1, wherein the routing connection circuits include first routing connection circuits configured to provide connections having a first impedance, and second routing connection circuits configured to provide connections having a second impedance that is less than the first impedance.

6. The integrated circuit of claim 1, wherein the local buses and global buses are shielded to reduce signal coupling therebetween.

7. The integrated circuit device of claim 1, wherein the reconfigurable analog signal switching fabric further includes at least one multiplexer (MUX) bus configured to be selectively connected to any of the external pins by the pin connection circuits and to at least one global and/or local bus by the routing connection circuits.

8. The integrated circuit of claim 1, further including a direct access circuit coupled to transfer data between the integrated circuit and a source external to the integrated circuit, wherein the digital system interconnect provides the analog routing data from the direct access circuit.

9. An integrated circuit comprising:

at least one processor circuit;

a plurality of analog circuit blocks; and

a dynamically or statically reconfigurable analog routing fabric configured to selectively connect and disconnect one or more of the plurality of analog circuit blocks with input/output (I/O) pins through I/O connection circuits in response to first analog routing data received from the at least one processor circuit from a programmable logic section comprising a plurality of digital programmable blocks formed in the integrated circuit; and

to selectively connect a first analog circuit block of the plurality of analog circuit blocks with a second analog circuit block of the plurality of analog circuit blocks to provide an analog function.

10. The integrated circuit of claim 9, wherein the dynamically or statically reconfigurable analog routing fabric is configured to selectively interconnect one or more of the plurality of analog circuit blocks with input/output (I/O) pins in response to analog routing data from a direct access circuit configured to transfer data between the integrated circuit and a source external to the integrated circuit.

11. The integrated circuit of claim 9, wherein the reconfigurable analog routing fabric includes connection circuits comprised of at least one of switch circuits configured to provide connections between single fabric points and any of multiple other fabric points, and multiplexer circuits configured to provide a single connection between a single fabric point and one of multiple other fabric points.

12. The integrated circuit of claim 11, further comprising at least one voltage generation circuit configured to:

generate at least one switch voltage outside a range of power supply voltages received by the integrated circuit; and

provide the at least one switch voltage to at least one connection circuit.

13. The integrated circuit of claim 9, wherein the reconfigurable analog routing fabric includes I/O connection circuits corresponding to each of a plurality of I/O pins, each I/O connection circuit configured to selectively connect its I/O pin to at least one of a multiplexer (MUX) bus and at least one of a plurality of global buses, wherein the global buses are connectable to the analog circuit blocks through the analog routing fabric.

14. The integrated circuit of claim 9, wherein the reconfigurable analog routing fabric includes routing connection circuits, each routing connection circuit corresponding to an analog circuit block, wherein each routing connection circuit is configured to selectively connect the corresponding analog circuit block to any of a plurality of local buses, wherein the local buses are connectable to I/O pins through the analog routing fabric.

15. The integrated circuit of claim 9, wherein the analog circuit blocks include at least two of an analog signal filter, a comparator, a capacitance sensing circuit, a switched capacitor circuit, a digital-to-analog converter, an analog-to-digital converter, and an operational amplifier.

16. A method comprising:

responsive to first routing data, configuring a reconfigurable analog routing fabric on an integrated circuit to selectively enable connections and disconnections between a plurality of input/output (I/O) pins and at least one of a plurality of global buses through I/O connection circuits coupled to the plurality of I/O pins; and

responsive to second routing data, configuring the reconfigurable analog routing fabric to selectively enable connections between at least one global bus and at least one of a plurality of analog circuit blocks of the integrated circuit; and

responsive to third routing data, configuring the reconfigurable analog routing fabric to selectively enable connections between a plurality of local buses and at least two of the plurality of analog circuit blocks to chain at the least two analog circuit blocks together to provide an analog function, wherein the routing data is dynamically or statically provided through digital circuits of the integrated circuit, wherein routing data is provided by a processor of the integrated circuit and a plurality of digital programmable blocks formed in the integrated circuit.

17. The method of claim 16, wherein the configuring of the reconfigurable analog fabric includes selectively enabling connections between the plurality of I/O pins and a multiplexer bus, and selectively enabling connections between the multiplexer bus and at least one of the analog circuit blocks.

18. The method of claim 16, wherein routing data is provided by a direct access circuit of the integrated circuit configured to transfer data between the integrated circuit and a location external to the integrated circuit.

19. The method of claim 16, further comprising, responsive to fourth routing data, configuring the reconfigurable analog fabric to selectively enable connections between the plurality of local buses and at least another two of the plurality of the analog circuit blocks to chain at least the other two analog circuit blocks together to provide another analog function.