Fan-out stacked system in package (SIP) having dummy dies and methods of making the same

• US 9,613,931 B2
• Filed: 04/30/2015
• Issued: 04/04/2017
• Est. Priority Date: 04/30/2015
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lin, Tsung-Shu, Chen, Hsien-Wei, Hsieh, Cheng-Chieh, Huang, Chang-Chia
• Primary Examiner(s): Maldonado, Julio J
• Assistant Examiner(s): Lu, Farun
• Application Number:
  US14/701,255
• Publication Number:
  US 20160322330A1
• Time in Patent Office: 705 Days
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/2518 being disposed on at least two different sides of the body, e.g. dual array
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/92244 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06548 Conductive via connections through the substrate, container, or encapsulation
• CPC Class Codes: H01L 2225/06555 Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
• CPC Class Codes: H01L 2225/06572 Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 2225/06589 Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/373 Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
• CPC Class Codes: H01L 23/3738 Semiconductor materials
• CPC Class Codes: H01L 23/4334 Auxiliary members in encapsulations H01L23/49568 takes precedence
• CPC Class Codes: H01L 23/49894 Materials of the insulating layers or coatings
• CPC Class Codes: H01L 23/5384 Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 25/043 Stacked arrangements of devices
• CPC Class Codes: H01L 25/0652 the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/074 : Stacked arrangements of non-apertured devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence

Abstract

An embodiment package includes a first fan-out tier, fan-out redistribution layers (RDLs) over the first fan-out tier, and a second fan-out tier over the fan-out RDLs. The first fan-out tier includes one or more first device dies and a first molding compound extending along sidewalls of the one or more first device dies. The second fan-out tier includes one or more second device dies bonded to fan-out RDLs, a dummy die bonded to the fan-out RDLs, and a second molding compound extending along sidewalls of the one or more second device dies and the dummy die. The fan-out RDLs electrically connects the one or more first device dies to the one or more second device dies, and the dummy die is substantially free of any active devices.

Claims

1. A package comprising:

a first fan-out tier comprising;

one or more first device dies; and

a first molding compound extending along sidewalls of the one or more first device dies;

fan-out redistribution layers (RDLs) over the first fan-out tier; and

a second fan-out tier over the fan-out RDLs, wherein the second fan-out tier comprises;

one or more second device dies bonded to the fan-out RDLs, wherein the fan-out RDLs electrically connects the one or more first device dies to the one or more second device dies;

a dummy die bonded to the fan-out RDLs, wherein the dummy die is substantially free of any active devices, wherein the one or more first device dies has a first total surface area, wherein the one or more second device dies and the dummy die has a second total surface area, and wherein a ratio of the first total surface area to the second total surface area is about 0.8 to about 1.2; and

a second molding compound extending along sidewalls of the one or more second device dies and the dummy die.

2. The package of claim 1, wherein a size of the dummy die, a material of the dummy die, or a combination thereof is in accordance with a desired effective coefficient of thermal expansion (CTE) of the second fan-out tier.

3. The package of claim 2, wherein the desired effective CTE is in accordance with an effective CTE of the first fan-out tier, an effective CTE of the fan-out RDLs, or a combination thereof.

4. The package of claim 1, wherein the one or more first device dies has a first total surface area, wherein the one or more second device dies has a third total surface area, wherein the first total surface area is greater than the third total surface area, and wherein the dummy die comprises silicon or glass.

5. The package of claim 1, wherein the one or more first device dies has a first total surface area, wherein the one or more second device dies has a second total surface area, wherein the first total surface area is less than the second total surface area, and wherein the dummy die comprises copper.

6. The package of claim 1, wherein the first fan-out tier has a first effective coefficient of thermal expansion (CTE), wherein the second fan-out tier has a second effective CTE, and wherein a ratio of the first effective CTE to the second effective CTE is about 0.9 to about 1.1.

7. The package of claim 1, wherein the dummy die is disposed between two of the one or more second device dies.

8. The package of claim 1, wherein at least one of the one or more second device dies is disposed between the dummy die and a second dummy die.

9. A package comprising:

a first device tier comprising;

one or more first device dies; and

a first molding compound encircling the one or more first device dies;

a second device tier comprising;

one or more second device dies;

a dummy die, wherein a size and material of the dummy die is in accordance with a desired effective coefficient of thermal expansion (CTE) of the second device tier; and

a second molding compound encircling the one or more second device dies and the dummy die, wherein a first total surface area of the one or more first device dies is greater than a second total surface area of the one or more second device dies, and wherein the dummy die has an effective coefficient of thermal expansion less than the second molding compound; and

fan-out redistribution layers (RDLs) between the first and second device tiers, wherein the one or more first device dies and the one or more second device dies are electrically connected to the fan-out RDLs.

10. The package of claim 9, wherein the one or more first device dies has a first total surface area, wherein the one or more second device dies and the dummy die has a second total surface area, and wherein a ratio of the first total surface area to the second total surface area is about 0.8 to about 1.2.

11. The package of claim 9, wherein the dummy die is electrically isolated from the one or more first device dies, the one or more second device dies, and the fan-out RDLs.

12. The package of claim 9, wherein the dummy die comprises silicon, glass, or a combination thereof.

13. The package of claim 9, wherein a first one of the one or more second device dies is disposed between the dummy die and an additional dummy die, and wherein the second molding compound also encircles the additional dummy die.

14. The package of claim 9, wherein the dummy die is disposed between a first one of the one or more second device dies and a second one of the one or more second device dies.

15. A package comprising:

a first semiconductor die;

a first molding compound encapsulating the first semiconductor die, wherein all semiconductor dies encapsulated by the first molding compound has a first combined surface area;

a second semiconductor die;

a dummy die adjacent the second semiconductor die, wherein the dummy die is substantially free of any functional circuitry;

a second molding compound encapsulating the second semiconductor die and the dummy die, wherein all semiconductor dies encapsulated by the second molding compound has a second combined surface area greater than the first combined surface area and wherein a coefficient of thermal expansion of the dummy die is greater than a coefficient of thermal expansion of the second molding compound; and

redistribution layers disposed between and electrically connecting the first semiconductor die and the second semiconductor die, wherein the redistribution layers further extend between the first molding compound and the second molding compound.

16. The package of claim 15 further comprising conductive vias extending through the first molding compound or the second molding compound.

17. The package of claim 15, wherein the dummy die is disposed between the second semiconductor die and a third semiconductor die, wherein the second molding compound further encapsulates the third semiconductor die.

18. The package of claim 15, wherein the second semiconductor die is disposed between the dummy die and an additional dummy die, wherein the additional dummy die is substantially free of any active circuits, and wherein the second molding compound further encapsulates the additional dummy die.

19. The package of claim 15, wherein the dummy die comprises a metal.