Split gate flash memory structure and method of making the split gate flash memory structure

• US 9,614,048 B2
• Filed: 06/17/2014
• Issued: 04/04/2017
• Est. Priority Date: 06/17/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Wu, Chang-Ming, Liu, Shih-Chang
• Primary Examiner(s): Page, Dale E
• Assistant Examiner(s): Wall, Vincent
• Application Number:
  US14/306,726
• Publication Number:
  US 20150364558A1
• Time in Patent Office: 1,022 Days
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/41725 Source or drain electrodes for field effect devices with monocrystalline semiconductor on source/drain region H01L29/0843
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7883 charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
• CPC Class Codes: H01L 2924/1438 Flash memory
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND

Abstract

A semiconductor structure of a split gate flash memory cell is provided. The semiconductor structure includes a semiconductor substrate including a source region and a drain region. Further, the semiconductor structure includes a floating gate, a word line, and an erase gate located over the semiconductor substrate between the source and drain regions. The floating gate is arranged between the word line and the erase gate. Even more, the semiconductor structure includes a dielectric disposed between the erase and floating gates. A thickness of the dielectric between the erase and floating gates is variable and increases towards the semiconductor substrate. A method of manufacturing the semiconductor structure is also provided.

Claims

1. A semiconductor structure of a split gate flash memory cell, said semiconductor structure comprising:

a semiconductor substrate including a source region and a drain region;

a floating gate, a word line, and an erase gate located over the semiconductor substrate, wherein the floating gate and the word line are located between the source and drain regions, wherein the floating gate is arranged between the word line and the erase gate and includes a ledge recessed below a top surface of the floating gate by a first vertical distance, and wherein a bottom surface of the floating gate is closer to the semiconductor substrate than the top surface of the floating gate; and

a dielectric structure made up of an upper portion and a lower portion which are disposed between the erase gate and the floating gate, wherein a sidewall of the upper portion and a sidewall of the lower portion contact a second ledge, which is recessed below the top surface of the floating gate by a second vertical distance that is greater than the first vertical distance, and wherein an edge portion of the erase gate overhangs and contacts the second ledge.

2. The semiconductor structure according to claim 1, further including:

a control gate disposed above the floating gate; and

a second dielectric structure disposed between the control gate and the floating gate.

3. The semiconductor structure according to claim 1, wherein a bottom surface of the word line is spaced below the bottom surface of the floating gate, and wherein a bottom surface of the erase gate is spaced above the bottom surface of the floating gate.

4. The semiconductor structure according to claim 1, wherein the sidewall of the upper portion and the sidewall of the lower portion contact the second ledge respectively at opposite sides of the second ledge, wherein the second ledge is planar, and wherein the sidewalls respectively of the lower portion and the upper portion are planar and contact the erase gate.

5. A semiconductor structure of a split gate flash memory cell, said semiconductor structure comprising:

a semiconductor substrate including a shared source/drain region and two individual source/drain regions, the shared and individual source/drain regions spaced along a surface of the semiconductor substrate with the shared source/drain region between the two individual source/drain regions; and

two split gate memory cells disposed between the two individual source/drain regions, wherein one of the split gate memory cells includes;

a floating gate, a word line, and an erase gate spaced over the surface, wherein the floating gate and the word line are arranged between the shared source/drain region and a corresponding individual source/drain region, and wherein the floating gate is arranged between the word line and the erase gate; and

a dielectric structure disposed between the erase gate and the floating gate, wherein a thickness of the dielectric structure between the erase gate and the floating gate is variable and increases towards the semiconductor substrate, wherein the dielectric structure has a stepped profile vertically between a top surface of the floating gate and a bottom surface of the floating gate, wherein the stepped profile is thicker at a bottom of the floating gate and comprises a ledge vertically spaced between the top surface of the floating gate and the bottom surface of the floating gate, wherein the ledge of the stepped profile extends laterally from a first sidewall of the dielectric structure to a second sidewall of the dielectric structure, wherein the first and second sidewalls of the dielectric structure contact the erase gate, and wherein a thickness of the dielectric structure is substantially uniform from the top surface of the floating gate to a top surface of the dielectric structure.

6. The semiconductor structure according to claim 5, wherein the dielectric structure includes a bottom region and a top region located atop the bottom region, the bottom region including a bottom surface approximately coplanar with the bottom surface of the floating gate and a first thickness greater than a second thickness of the top region, and the top region including a top surface approximately coplanar with the top surface of the floating gate.

7. The semiconductor structure according to claim 6, wherein the second thickness of the top region is uniform and the first thickness of the bottom region is uniform.

8. The semiconductor structure according to claim 6, wherein the floating gate comprises a planar sidewall abutting the top and bottom regions, and wherein the erase gate comprises a non-planar sidewall abutting the top and bottom regions.

9. The semiconductor structure according to claim 5, further comprising:

a control gate disposed above the floating gate; and

a second dielectric structure disposed between the control gate and the floating gate.

10. The semiconductor structure according to claim 5, wherein the floating gate comprises a ledge recessed below the top surface of the floating gate, and wherein the stepped profile is arranged between the ledge of the floating gate and the bottom surface of the floating gate.

11. The semiconductor structure according to claim 5, wherein the top surface of the dielectric structure is coplanar with a top surface of the erase gate.

12. The semiconductor structure according to claim 5, wherein the first sidewall of the dielectric structure extends continuously to a top surface of the erase gate, wherein the second sidewall of the dielectric structure extends continuously to a bottom surface of the erase gate, and wherein the bottom surface of the erase gate is concave and arcs between opposite sides of the erase gate.

13. The semiconductor structure according to claim 12, wherein the ledge of the stepped profile contacts a lower surface of the erase gate that overhangs the ledge of the stepped profile, and wherein the ledge of the stepped profile and the lower surface of the erase gate are planar.

14. The semiconductor structure according to claim 12, further comprising:

a second dielectric structure arranged between the word line and the floating gate, wherein the second dielectric structure has a first lateral thickness between the ledge of the floating gate and the bottom surface of the floating gate, and wherein the first lateral thickness of the second dielectric structure is greater than a first maximum lateral thickness of the dielectric structure between the ledge of the floating gate and the bottom surface of the floating gate.

15. The semiconductor structure according to claim 14, wherein the second dielectric structure has a second lateral thickness between the ledge of the floating gate and a top surface of the erase gate, wherein the second lateral thickness of the second dielectric structure is greater than the first lateral thickness of the second dielectric structure, wherein the dielectric structure has a second maximum lateral thickness between the ledge of the floating gate and the top surface of the erase gate, and wherein the second maximum lateral thickness of the dielectric structure is greater than the first maximum lateral thickness of the dielectric structure.