Active non-volatile memory post-processing

• US 9,619,430 B2
• Filed: 02/24/2012
• Issued: 04/11/2017
• Est. Priority Date: 02/24/2012
• Status: Active Grant

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Inventors: Kannan, Sudarsun, Milojicic, Dejan S., Talwar, Vanish
• Primary Examiner(s): Dudek, Jr., Edward
• Assistant Examiner(s): RUSSELL, ANDREW D
• Application Number:
  US13/404,619
• Publication Number:
  US 20130227194A1
• Time in Patent Office: 1,873 Days
• Field of Search: 711103
• CPC Class Codes: G06F 15/173 using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
• CPC Class Codes: G06F 15/7821 Tightly coupled to memory, e.g. computational memory, smart memory, processor in memory
• CPC Class Codes: G06F 3/067 Distributed or networked storage systems, e.g. storage area networks [SAN], network attached storage [NAS]
• CPC Class Codes: G06F 9/3877 using a slave processor, e.g. coprocessor peripheral processor G06F13/12; vector processor G06F15/8053

Abstract

A computing node includes an active Non-Volatile Random Access Memory (NVRAM) component which includes memory and a sub-processor component. The memory is to store data chunks received from a processor core, the data chunks comprising metadata indicating a type of post-processing to be performed on data within the data chunks. The sub-processor component is to perform post-processing of said data chunks based on said metadata.

Claims

1. A computing node comprising:

an active Non-Volatile Random Access Memory (NVRAM) component comprising;

memory to store data chunks received from a processor core, said data chunks comprising metadata indicating a type of post-processing to be performed on data within said data chunks; and

a sub-processor component to perform post-processing of said data chunks based on said metadata.

2. The computing node of claim 1, wherein said active NVRAM component comprises a module component communicatively coupled to said processor core.

3. The computing node of claim 1, wherein said computing node is one of multiple computing nodes also comprising an active NVRAM component, each of said multiple computing nodes acting in concert to execute a process.

4. The computing node of claim 3, wherein said process being executed by said multiple computing nodes is to assign an order identifier to data chunks.

5. The computing node of claim 4, wherein said sub-processor component is to process said data chunks within said memory in an order according to an active global queue.

6. The computing node of claim 5, wherein said active global queue reflects use of a balanced tree data structure to distribute processing of said data chunks across said multiple computing nodes.

7. The computing node of claim 1, wherein said post-processing comprises at least one of:

data compression, indexing and data sorting.

16. The computing node of claim 1, further comprising an output for connection to long-term persistent storage when said data chucks are stored following said post-processing.

17. The computing node of claim 1, further comprising a global queue, wherein said sub-processor is programmed to determine if a next data chunk to be post processed according to said global queue is within the memory of NVRAM component of the sub-processor and, if so, will fetch and post-process that data chunk according to the metadata of that data chunk.

18. The computing node of claim 1, wherein said memory receives said data chunks from said processor core using memory semantics rather than file semantics.

19. The computing node of claim 1, wherein the metadata indicates whether the data of the corresponding data chunk is to be sorted, reformatted or compressed and how the data of the corresponding data chunk is to be sorted, reformatted or compressed.

20. The computing node of claim 1, further comprising a locking mechanism to prevent conflicts if multiple processor cores attempt to write data to said NVRAM component.

8. A method for post-processing, the method comprising:

with a computing node, storing data chunks received from a processor core into a memory of an active Non-Volatile Random Access Memory (NVRAM) component, said data chunks comprising metadata indicating a type of post-processing to be performed on data within said data chunks; and

with a sub-processor component of said active NVRAM component, performing post-processing of said data chunks based on said metadata.

9. The method of claim 8, wherein said active NVRAM component comprises a module component communicatively coupled to said processor core.

10. The method of claim 8, wherein said computing node is one of multiple computing nodes each comprising an active NVRAM component, each of said multiple computing nodes acting in concert to execute a process.

11. The method of claim 10, further comprising, with an application being executed by said multiple computing nodes, assigning an order identifier to data chunks.

12. The method of claim 11, further comprising, with said sub-processor component, processing said data chunks within said memory in an order according to an active global queue.

13. The method of claim 12, wherein said active global queue reflects use of a balanced tree data structure to distribute processing of said data chunks across said multiple computing nodes.

14. The method of claim 8, wherein said post-processing comprises at least one of:

data compression and sorting.

15. A computing system comprising:

a number of computing nodes, each node comprising;

an active Non-Volatile Random Access Memory (NVRAM) component comprising;

memory to store Input/Output (I/O) data chunks received from a processor core, said data chunks comprising metadata indicating a type of post-processing to be performed on data within said data chunks; and

a sub-processor component to perform post-processing of said I/O data based on said metadata; and

a global active queue to use a balanced tree data structure to distribute processing of said data chunks across said number of computing nodes according to an order identifier assigned to said data chunks.