Method for manufacturing thin film transistor, and thin film transistor thereof

• US 9,620,606 B2
• Filed: 06/08/2016
• Issued: 04/11/2017
• Est. Priority Date: 11/15/2012
• Status: Active Grant

• Current Assignee: Beijing BOE Display Technology Co Ltd (BOE Technology Group Co., Ltd.), BOE Technology Group Co., Ltd.
• Original Assignee: Beijing BOE Display Technology Co Ltd (BOE Technology Group Co., Ltd.), BOE Technology Group Co., Ltd.
• Inventors: He, Zongze
• Primary Examiner(s): Rizkallah, Kimberly
• Assistant Examiner(s): Turner, Brian
• Application Number:
  US15/176,388
• Publication Number:
  US 20160284809A1
• Time in Patent Office: 307 Days
• Field of Search: 257 57, 257 59, 257E33004, 257665, 257291, 438149
• CPC Class Codes: G02F 1/134309 characterised by their geometrical arrangement
• CPC Class Codes: G02F 1/13439 characterised by their electrical, optical, physical properties; materials therefor; method of making
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02576 N-type
• CPC Class Codes: H01L 21/02592 amorphous
• CPC Class Codes: H01L 27/1222 with a particular composition, shape or crystalline structure of the active layer
• CPC Class Codes: H01L 27/1262 with a particular formation, treatment or coating of the substrate
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/495 the conductor material next to the insulator being a simple metal, e.g. W, Mo H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/6675 Amorphous silicon or polysilicon transistors
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

The present disclosure relates to the field of liquid crystal display, and provides a method for manufacturing a TFT and the TFT thereof. The TFT includes: a base substrate; a gate electrode with a three-dimensional structure formed on the base substrate; a gate insulating layer for completely covering a top face and two side faces of the gate electrode; a semiconductor layer for completely covering a top face and two side faces of the gate insulating layer; a buffer layer for covering a top face and two side faces of the semiconductor layer at two ends of the semiconductor layer; and source and drain electrodes for completely covering a top face and two side faces of the buffer layer, wherein the semiconductor layer of the TFT is of a three-dimensional structure.

Claims

1. A method for manufacturing a thin film transistor (TFT), comprising:

providing a base substrate;

forming a gate electrode with a three-dimensional structure on the base substrate;

forming a gate insulating layer for completely covering a top face and two side faces of the gate electrode;

forming a semiconductor layer for completely covering a top face and two side faces of the gate insulating layer;

forming a buffer layer at two ends of the semiconductor layer for covering a top face and two side faces of the semiconductor layer; and

forming a source electrode and a drain electrode for completely covering a top face and two side faces of the buffer layer,

wherein a three-dimensional structure of the TFT comprises an X-axis direction, a Y-axis direction and a Z-axis direction orthogonal to each other, a positive X-axis direction represents a transmission direction of carriers of the TFT, and the Y-axis direction is perpendicular to a plane where the base substrate is located,

the buffer layer is formed at the two ends of the semiconductor layer in the X-axis direction, the source electrode and the drain electrode cover the buffer layer at the two ends of the semiconductor layer, and a portion of the top face of the semiconductor layer between the source electrode and the drain electrode and portions of the two side faces of the semiconductor layer between the source electrode and the drain electrode form channel regions, and

the two side faces of each of the gate insulating layer, the semiconductor layer and the buffer layer are located at two sides of the gate electrode in the Z-axis direction.

2. The method according to claim 1, wherein the three-dimensional structure of the gate electrode is a cuboid or cube.

3. The method according to claim 2, wherein the step of forming the gate electrode with the three-dimensional structure on the base substrate comprises:

depositing a first metal layer on the base substrate; and

treating the first metal layer by a patterning process to form the gate electrode with the three-dimensional structure.

4. The method according to claim 3, wherein the first metal layer is made of indium tin oxide (ITO), or a metal selected from the group consisting of Cr, Mo, Al, Nd, Mo, W, Ti, Ta and Cu, or an alloy thereof.

5. The method according to claim 2, wherein the step of forming a gate insulating layer for completely covering a top face and two side faces of the gate electrode comprises:

depositing an insulating material on the base substrate on which the gate electrode with a cuboid structure is formed; and

treating the insulating material by a patterning process to form the gate insulating layer on the top face and the two side faces of the gate electrode.

6. The method according to claim 2, wherein the step of forming a semiconductor layer for completely covering a top face and two side faces of the gate insulating layer comprises:

depositing a semiconductor material on the base substrate on which the gate insulating layer is formed; and

treating the semiconductor material by a patterning process to form the semiconductor layer on the top face and the two side faces of the gate insulating layer.

7. The method according to claim 2, wherein the step of forming a buffer layer at two ends of the semiconductor layer for covering a top face and two side faces of the semiconductor layer comprises:

depositing an N+ amorphous silicon material on the base substrate on which the semiconductor layer is formed; and

treating the N+ amorphous silicon material layer by a patterning process to form the buffer layer on the top face and the two side faces of the semiconductor layer at the two ends of the semiconductor layer.

8. The method according to claim 2, wherein the step of forming the source electrode and the drain electrode for completely covering the top face and the two side faces of the buffer layer comprises:

depositing a second metal layer on the base substrate on which the buffer layer is formed; and

treating the second metal layer by a patterning process to form the source and drain electrodes on the top face and the two side faces of the buffer layer.

9. The method according to claim 8, wherein the second metal layer is made of a metal selected from the group consisting of Cr, Mo, Al, Nd, Mo, W, Ti, Ta and Cu, or an alloy thereof.

10. The method according to claim 1, wherein a three-dimensional structure of the semiconductor layer is an inverted-U slot structure covering the gate electrode.

11. The method according to claim 10, wherein a portion of the semiconductor layer between the source and drain electrodes forms a channel, a length of the channel is equal to a distance between the source and drain electrodes, and a width of the channel≧

(a width of the gate electrode in the Z-axis direction+2*a height of the gate electrode in the Y-axis direction).

12. A thin film transistor (TFT), comprising:

a base substrate;

a gate electrode with a three-dimensional structure formed on the base substrate;

a gate insulating layer for completely covering a top face and two side faces of the gate electrode;

a semiconductor layer for completely covering a top face and two side faces of the gate insulating layer;

a buffer layer for covering a top face and two side faces of the semiconductor layer at two ends of the semiconductor layer; and

a source electrode and a drain electrode for completely covering a top face and two side faces of the buffer layer,

wherein a three-dimensional structure of the TFT comprises an X-axis direction, a Y-axis direction and a Z-axis direction orthogonal to each other, a positive X-axis direction represents a transmission direction of carriers of the TFT, and the Y-axis direction is perpendicular to a plane where the base substrate is located,

the buffer layer is formed at the two ends of the semiconductor layer in the X-axis direction, the source electrode and the drain electrode cover the buffer layer at the two ends of the semiconductor layer, and a portion of the top face of the semiconductor layer between the source electrode and the drain electrode and portions of the two side faces of the semiconductor layer between the source electrode and the drain electrode form channel regions, and

the two side faces of each of the gate insulating layer, the semiconductor layer and the buffer layer are located at two sides of the gate electrode in the Z-axis direction.

13. The TFT according to claim 12, wherein the three-dimensional structure of the gate electrode is a cuboid or cube.

14. The TFT according to claim 13, wherein a portion of the semiconductor layer between the source and drain electrodes forms a channel, a length of the channel is equal to a distance between the source and drain electrodes, and a width of the channel≧

(a width of the gate electrode in the Z-axis direction+2*a height of the gate electrode in the Y-axis direction).

15. The TFT according to claim 14, wherein the channel of the TFT comprises at least three electronic gates.

16. The TFT according to claim 12, wherein a three-dimensional structure of the semiconductor layer is an inverted-U slot structure covering the gate electrode.