Power-gating media decoders to reduce power consumption

• US 9,632,561 B2
• Filed: 06/28/2007
• Issued: 04/25/2017
• Est. Priority Date: 06/28/2007
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Lindahl, Aram, Guetta, Anthony J.
• Primary Examiner(s): Huynh, Kim
• Assistant Examiner(s): Chang, Eric
• Application Number:
  US11/770,446
• Publication Number:
  US 20090003115A1
• Time in Patent Office: 3,589 Days
• Field of Search: 713320, 713300
• CPC Class Codes: G06F 1/3225 of memory devices
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Embodiments of a system that reduces power consumption by power-gating media decoders are described. During operation of the system, a decoder circuit receives encoded audio data and outputs corresponding decoded audio data to a memory, which is electrically coupled to the decoder circuit. Moreover, control logic, which is electrically coupled to the memory and the decoder circuit, provides commands to the memory and the decoder circuit that selectively disable at least a portion of the memory based on an amount of decoded audio data in the memory.

Claims

1. A system, comprising:

a first memory configured to store encoded audio data;

a second memory configured to store decoded audio data;

a decoder circuit configured to receive encoded audio data from the first memory and to output decoded audio data to the second memory; and

control logic electrically coupled to the first memory, the second memory, and the decoder circuit, the control logic configured to receive information of an amount of encoded audio data in the first memory and an amount of decoded audio data in the second memory and to—

selectively disable and enable at least a portion of the first memory by decoupling and coupling a power signal to the at least a portion of the first memory based at least in part on the amount of encoded audio data in the first memory,

selectively disable and enable at least a portion of the second memory by decoupling and coupling a power signal to the at least a portion of the second memory based at least in part on the amount of decoded audio data in the second memory, and

selectively disable and enable the decoder circuit based at least in part on the amount of encoded audio data in the first memory and the amount of decoded audio data in the second memory.

2. The system of claim 1, wherein the control logic is configured to select a duty cycle or a period for the selective disabling.

3. The system of claim 1, wherein the control logic is further configured to selectively decouple and couple a clock signal used by the at least a portion of the first memory or the at least a portion of the second memory.

4. The system of claim 1, wherein the selective disabling is based on transient power consumption associated with disabling the at least a portion of the first memory or the at least a portion of the second memory.

5. The system of claim 1, wherein the control logic is further configured to selectively disable at least one of the at least a portion of the first memory, the at least a portion of the second memory, and the decoder circuit when the amount of decoded audio data in the second memory exceeds a first pre-determined value.

6. The system of claim 1, wherein the control logic is further configured to:

selectively disable at least one of the at least a portion of the first memory, the at least a portion of the second memory, and the decoder circuit when the amount of decoded audio data in the second memory exceeds a first pre-determined value, and

selectively enable at least one of the at least a portion of the first memory, the at least a portion of the second memory, and the decoder circuit when the amount of decoded audio data in the second memory is less than a second pre-determined value.

7. The system of claim 6, wherein the first pre-determined value is different from the second pre-determined value.

8. The system of claim 1, wherein the selective disabling of the at least a portion of the second memory is based on an amount of audio data remaining to be decoded or a rate of decoding of the audio data.

9. The system of claim 1, wherein the selective disabling of the at least a portion of the second memory is based on an amount of memory allocated for the decoded audio data.

10. The system of claim 1, wherein the control logic is further configured to abort the selective disabling of the at least a portion of the second memory when a mode of playing the decoded audio data is changed or when a new mode of playing increases consumption of the decoded audio data in the second memory.

11. The system of claim 1, wherein the control logic is further configured to abort the selective disabling of the at least a portion of the second memory when an amount of memory allocated for the decoded audio data is changed.

12. The system of claim 1, wherein the control logic is further configured to abort the selective disabling of the at least a portion of the second memory when an end of a file associated with the decoded audio data is detected.

13. The system of claim 1, wherein the control logic is further configured to abort the selective disabling of the at least a portion of the second memory based on a state of the decoder circuit.

14. A method for conserving power in an electronic device, comprising the use of:

a first memory;

a second memory;

a decoder circuit, wherein the decoder circuit is configured to receive encoded audio data from the first memory and provide decoded audio data to the second memory; and

control logic, wherein the control logic is electrically coupled to the first memory, the second memory, and the decoder circuit and wherein the control logic is configured to receive information of the amount of encoded audio data in the first memory and the amount of decoded audio data in the second memory and to—

selectively disable and enable at least a portion of the first memory by decoupling and coupling a power signal to the at least a portion of the first memory based at least in part on the amount of encoded audio data in the first memory,

selectively disable and enable at least a portion of the second memory by decoupling and coupling a power signal to the at least a portion of the second memory based at least in part on the amount of decoded audio data in the second memory, and

selectively disable and enable the decoder circuit based at least in part on the amount of encoded audio data in the first memory and the amount of decoded audio data in the second memory.

15. A system configured to execute instructions to conserve power, comprising:

a processor;

a memory;

an instruction fetch unit within the processor configured to fetch;

instructions for receiving information from a first memory and a decoder circuit, the decoder circuit being configured to receive encoded audio data from the first memory, and the information indicating an amount of encoded audio data in the first memory;

instructions for receiving information from a second memory and the decoder circuit, the decoder circuit further configured to provide decoded audio data to the second memory, and the information further indicating an amount of decoded audio data in the second memory;

instructions for determining whether to selectively disable or enable at least a portion of the first memory by decoupling and coupling a power signal to the at least a portion of the first memory based at least in part on the amount of encoded coded audio data in the first memory;

instructions for determining whether to selectively disable or enable at least a portion of the second memory by decoupling and coupling a power signal to the at least a portion of the first memory based at least in part on the amount of decoded audio data in the second memory;

instructions for determining whether to selectively disable or enable the decoder circuit based at least in part on the amount of encoded audio data in the first memory and the decoded audio data in the second memory; and

instructions for providing commands to the first memory, the second memory and the decoder circuit that selectively disables and enables the at least a portion of the first memory, the at least a portion of the second memory, and the decoder circuit; and

an execution unit within the processor configured to execute the instructions for receiving, the instructions for determining, and the instructions for providing the commands.