Packages with interposers and methods for forming the same

• US 9,633,869 B2
• Filed: 08/16/2013
• Issued: 04/25/2017
• Est. Priority Date: 08/16/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chiu, Sao-Ling, Hsu, Kuo-Ching, Wu, Wei-Cheng, Huang, Ping-Kang, Hou, Shang-Yun, Jeng, Shin-Puu, Yu, Chen-Hua
• Primary Examiner(s): Stark, Jarrett
• Assistant Examiner(s): Ausar-El, Charles N
• Application Number:
  US13/968,730
• Publication Number:
  US 20150048503A1
• Time in Patent Office: 1,348 Days
• Field of Search: 257738
• CPC Class Codes: H01L 21/4853 Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
• CPC Class Codes: H01L 21/4857 Multilayer substrates multilayer metallisation on monolayer substrate H01L21/4846
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/147 Semiconductor insulating substrates semiconductor conductive substrates H01L23/4926
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/3135 Double encapsulation or coating and encapsulation
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49838 : Geometry or layout
• CPC Class Codes: H01L 23/5384 : Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 23/562 : Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18161 : of a flip chip
• CPC Class Codes: H01L 2924/3511 : Warping

Abstract

A package structure includes an interposer, a die over and bonded to the interposer, and a Printed Circuit Board (PCB) underlying and bonded to the interposer. The interposer is free from transistors therein (add transistor), and includes a semiconductor substrate, an interconnect structure over the semiconductor substrate, through-vias in the silicon substrate, and redistribution lines on a backside of the silicon substrate. The interconnect structure and the redistribution lines are electrically coupled through the through-vias.

Claims

1. A package structure comprising:

an interposer free from active devices therein, the interposer comprising;

a silicon substrate;

an interconnect structure on a front side of the silicon substrate;

through-vias in the silicon substrate;

solder regions electrically coupled to the through-vias; and

a first molding material molding a portion of each of the solder regions therein, wherein no portion of the first molding material is at a same level as the silicon substrate, and wherein the first molding material has properties of being applicable in a liquid state and curable into a solid state;

a die over and bonded to the interposer;

a Printed Circuit Board (PCB) underlying and bonded to the interposer through the solder regions; and

a second molding material encircling the die and comprising an epoxy, with an entirety of the first molding material and an entirety of the second molding material being on opposite sides of the silicon substrate, wherein the second molding material comprises edges aligned to corresponding edges of the silicon substrate of the interposer, and the first molding material and the second molding material are on opposite sides of the silicon substrate of the interposer.

2. The package structure of claim 1 further comprising an underfill in physical contact with both the PCB and the first molding material, wherein the underfill has slanted edges.

3. The package structure of claim 2, wherein the underfill has a top surface in contact with a bottom surface of the first molding material, and a bottom surface in contact with the PCB.

4. The package structure of claim 2, wherein the underfill has a bottom surface in physical contact with metal features in the PCB, wherein the metal features are also in contact with the solder regions.

5. The package structure of claim 2, wherein the interposer further comprises:

a first dielectric layer on a back side of, and in contact with, the silicon substrate, wherein the through-vias continuously extend from the silicon substrate into the first dielectric layer; and

a second dielectric layer having a top surface in contact with a bottom surface of the first dielectric layer, wherein the underfill contacts a sidewall of the second dielectric layer.

6. The package structure of claim 1, wherein the edges of the first molding material and the second molding material are perpendicular to a major surface of the silicon substrate.

7. The package structure of claim 1, wherein the interposer is directly bonded to the PCB, and no package substrate is bonded between the interposer and the PCB.

8. The package structure of claim 1, wherein edges of the first molding material and the second molding material are aligned to respective edges of the silicon substrate.

9. A package structure comprising:

an interposer free from transistors therein, wherein the interposer comprises;

a silicon substrate;

an interconnect structure over the silicon substrate;

a first dielectric layer underlying and in contact with the silicon substrate; and

through-vias continuously extending from the silicon substrate into the first dielectric layer, wherein an end of one of the through-vias is level with a bottom surface of the first dielectric layer;

a device die over and bonded to the interposer;

a Printed Circuit Board (PCB) underlying and bonded to the interposer through solder regions, wherein no package substrate is bonded between the interposer and the PCB;

a first molding material encircling the device die, wherein the first molding material comprises edges aligned to corresponding edges of the silicon substrate of the interposer;

a second molding material encapsulating portions of the solder regions therein, wherein an entirety of the first molding material and an entirety of the second molding material are on opposite sides of the interposer, and the second molding material does not have any portion at a same level as the silicon substrate of the interposer, and the second molding material has properties of being applicable in a liquid state and curable into a solid state; and

an underfill in a gap between the PCB and the interposer.

10. The package structure of claim 9, wherein the solder regions are in physical contact with metal features of the PCB, and the underfill has a bottom surface in physical contact with the metal features of the PCB.

11. The package structure of claim 9, wherein edges of the first molding material and the second molding material are aligned to respective edges of the silicon substrate.

12. The package structure of claim 9, wherein the device die and the first dielectric layer are on opposite sides of the silicon substrate, and the interposer further comprises a second dielectric layer underlying and in contact with the first dielectric layer, and the underfill contacts a sidewall of the second dielectric layer.

13. A package structure comprising:

an interposer free from active devices therein, wherein the interposer comprises;

a silicon substrate;

an interconnect structure over the silicon substrate;

a first dielectric layer underlying, and in contact with, the silicon substrate;

through-vias in the silicon substrate, wherein the through-vias continuously extend from the silicon substrate into the first dielectric layer, wherein an end of one of the through-vias is level with a bottom surface of the first dielectric layer; and

a second dielectric layer underlying and in contact with the first dielectric layer;

a device die over and bonded to the interposer;

a first molding material molding the device die therein, wherein the first molding material comprises a bottom surface contacting the interposer, and edges aligned to corresponding edges of the interposer, wherein a top surface of the first molding material is coplanar with a top surface of the device die;

a second molding material, wherein an entirety of the first molding material and an entirety of the second molding material are on opposite sides of the interposer, and the second molding material does not have any portion at a same level as the silicon substrate of the interposer;

a Printed Circuit Board (PCB);

solder regions physically bonding the interposer to the PCB, with portions of the solder regions encapsulated in the second molding material; and

an underfill in a gap between the PCB and the interposer, wherein the underfill has a substantially vertical sidewall in contact with a sidewall of the second dielectric layer and a sidewall of the second molding material, and a slanted sidewall opposite to the substantially vertical sidewall.

14. The package structure of claim 13, wherein the underfill further contacts a metal feature in the PCB, with the metal feature joined to a solder region in the solder regions.

15. The package structure of claim 13, wherein the sidewall of the second dielectric layer has an upper portion higher than a top end of the underfill, and a lower portion in contact with the underfill.

16. The package structure of claim 13, wherein the interconnect structure comprises a low-k dielectric layer.

17. The package structure of claim 13, wherein edges of the first dielectric layer are aligned to corresponding edges of the first molding material.

18. The package structure of claim 13, wherein edges of the first molding material and the second molding material are aligned to respective edges of the silicon substrate.

19. The package structure of claim 13, wherein the device die and the first dielectric layer are on opposite sides of the silicon substrate.

20. The package structure of claim 13 further comprising redistribution lines in the second dielectric layer, wherein surfaces of the redistribution lines and a surface of the second dielectric layer are coplanar with each other to form a first planar surface, and the second molding material has a second planar surface in contact with the first planar surface.