Contact for semiconductor fabrication

• US 9,634,013 B2
• Filed: 10/16/2014
• Issued: 04/25/2017
• Est. Priority Date: 10/16/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Liaw, Jhon Jhy
• Primary Examiner(s): Parker, Kenneth
• Assistant Examiner(s): Kilpatrick, Warren H
• Application Number:
  US14/516,278
• Publication Number:
  US 20160111430A1
• Time in Patent Office: 922 Days
• Field of Search: 257329, 257353
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/6681 using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element

Abstract

A semiconductor device includes a substrate, a fin structure on the substrate, the fin structure comprising a doped region, a first gate over the fin structure, the first gate positioned adjacent the doped region, the first gate having a spacer on a first side and having no spacer on a second side between the gate and the doped region, and a conductive plug that contacts the doped region and a top of the gate.

Claims

1. A semiconductor device comprising:

a substrate;

a fin structure on the substrate, the fin structure comprising a doped region;

a first gate over the fin structure, the first gate positioned adjacent the doped region, the first gate having a spacer on a first side and having no spacer on a second side between the gate and the doped region, the first gate including a gate dielectric layer disposed over the fin structure and a gate electrode disposed over the gate dielectric layer and physically contacting the gate dielectric layer, the gate dielectric layer extending along opposing sidewalls of the gate electrode towards a top of the first gate without extending to the top of the first gate on the second side of the first gate; and

a conductive plug that physically contacts the doped region, the gate dielectric layer, one of the sidewalls of the gate electrode and the top of the first gate.

2. The device of claim 1, wherein the first gate comprises a metal replacement gate.

3. The device of claim 2, wherein the gate dielectric layer includes a high-k dielectric layer physically contacting the fin structure directly under the gate electrode and extending along.

4. The device of claim 1, further comprising, a second gate positioned adjacent the doped region opposite the first gate, the second gate having spacers on both sides.

5. The device of claim 3, wherein the conductive plug extends to a spacer of the second gate.

6. The device of claim 3, wherein the first gate and second gate are pull-up transistors of a Static Random Access Memory (SRAM) cell.

7. The device of claim 1, wherein the doped region comprises a doped epitaxial region.

8. The device of claim 1, further comprising a silicide layer formed on the doped region between the doped region and the conductive plug.

9. The device of claim 1, wherein the first gate is positioned at a longitudinal end of the fin structure.

10. The device of claim 1, wherein the fin structure is formed over an N-well in the substrate.

11. The device of claim 10, wherein the first gate is an elongated gate that serves as a gate to a pull-up device over the N-well and a pull-down device formed over a P-well in the substrate.

12. A semiconductor device comprising:

a substrate;

a fin structure formed on the substrate, the fin structure comprising a doped region;

a first gate on a first side of the doped region, the first gate including a gate dielectric layer disposed over the fin structure and a gate electrode disposed over the gate dielectric layer and physically contacting the gate dielectric layer, the gate dielectric layer extending along opposing sidewalls of the gate electrode towards a top of the first gate;

a second gate on a second side of the doped region, the second side being opposite the first side, the second gate having spacers on both sides;

a self-aligned contact between the first gate and the second gate, the self-aligned contact physically contacting the gate dielectric layer and one of the sidewalls of the gate electrode; and

a butt contact that is in direct connection with the top of the first gate and the self-aligned contact.

13. The device of claim 12, wherein the butt contact is in direct contact with the top of the self-aligned contact.

14. The device of claim 12, wherein the top of the self-aligned contact is at a different height than a top of the first gate.

15. The device of claim 12, wherein the self-aligned contact is in direct contact with one of the spacers from the second gate.

16. The device of claim 12, further comprising, a silicide layer between the doped region and the self-aligned contact.

17. The device of claim 12, wherein the gate dielectric layer includes a high-k dielectric layer physically contacting the fin structure directly under the gate electrode.

18. A method for forming a semiconductor device, the method comprising:

providing a substrate;

forming a fin structure on the substrate;

forming a dummy gate over the fin structure;

forming sidewall spacers on both sides of the dummy gate;

forming a doped region within the fin structure, the doped region being formed adjacent the dummy gate;

replacing the dummy gate with a gate, the gate including a gate dielectric layer and metal gate electrode disposed over the gate dielectric layer and physically contacting the gate dielectric layer, the gate dielectric layer extending along opposing sidewalls of the metal gate electrode towards a top of the gate;

removing a spacer from a first side of the gate to expose the gate dielectric layer, the first side being between the gate and the doped region;

removing a portion of the gate dielectric layer to expose one of the sidewalls of the metal gate electrode; and

forming a conductive plug that physically contacts the doped region, the gate dielectric layer, the one of the sidewalls of the metal gate electrode, and a top of the gate.

19. The method of claim 18, further comprising, forming a second gate adjacent the doped region opposite the first gate, the second gate comprising spacers on both sides, wherein the conductive plug extends to one of the spacers of the second gate.

20. The method of claim 18, further comprising forming a shallow trench isolation feature in the substrate, and

wherein forming sidewall spacers on both sides of the dummy gate includes forming the spacer directly on the fin structure such that the spacer physically contacts the fin structure and forming another spacer on a second side of the dummy gate such that the another spacer physically contacts the shallow trench isolation feature.