Semiconductor apparatus

• US 9,638,754 B2
• Filed: 10/28/2014
• Issued: 05/02/2017
• Est. Priority Date: 07/08/2014
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: Jang, Soo Young
• Primary Examiner(s): Nguyen, Tung X
• Application Number:
  US14/525,333
• Publication Number:
  US 20160011263A1
• Time in Patent Office: 917 Days
• CPC Class Codes: G01R 31/31701 Arrangements for setting the Unit Under Test [UUT] in a test mode
• CPC Class Codes: G01R 31/31723 Hardware for routing the test signal within the device under test to the circuits to be tested, e.g. multiplexer for multiple core testing, accessing internal nodes routing the test signal to or from the device under test G01R31/31926
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G01R 31/3187 Built-in tests

Abstract

A semiconductor apparatus includes a test entry control block configured to generate a plurality of trigger signals and a reset signal according to a test setting command and addresses; and a test entry signal generation block configured to enable a test entry signal when the plurality of trigger signals are sequentially enabled.

Claims

1. A semiconductor apparatus comprising:

a test entry control block configured to enable a plurality of trigger signals in a predetermined order in response to a test setting command and addresses successively inputted, and enable a reset signal when another command other than the test setting command is inputted; and

a test entry signal generation block configured to sequentially enable a plurality of pre-test entry signals when the plurality of trigger signals are enabled in the predetermined order, and enable a test entry signal when a final pre-test entry signal among the plurality of pre-test entry signals is enabled,

wherein the final pre-test entry signal is enabled when all the plurality of pre-test entry signals are enabled.

2. The semiconductor apparatus according to claim 1, wherein the test entry control block comprises:

a trigger signal generation unit configured to sequentially enable the plurality of trigger signals when the addresses inputted simultaneously with the test setting command are the same as pluralities of fixed codes; and

a reset signal generation unit configured to enable the reset signal when a part of the pluralities of fixed codes and the addresses are different from each other, or enable the reset signal when the another command other than the test setting command is inputted.

3. The semiconductor apparatus according to claim 2,

wherein the pluralities of fixed codes comprise first to third fixed codes,

wherein the plurality of trigger signals comprise first to third trigger signals, and

wherein the trigger signal generation unit comprises:

a first enable section configured to enable the first trigger signal when the addresses inputted simultaneously with the test setting command are the same as the first fixed codes;

a second enable section configured to enable the second trigger signal when the addresses inputted simultaneously with the test setting command are the same as the second fixed codes; and

a third enable section configured to enable the third trigger signal when the addresses inputted simultaneously with the test setting command are the same as the third fixed codes.

4. The semiconductor apparatus according to claim 3,

wherein the plurality of pre-test entry signals comprise first and second pre-test entry signals, and

wherein the reset signal generation unit comprises:

a first reset enable signal generating section configured to enable a first reset enable signal when the addresses inputted simultaneously with the test setting command are different from the second fixed codes in a state in which the first pre-test entry signal is enabled;

a second reset enable signal generating section configured to enable a second reset enable signal when the addresses inputted simultaneously with the test setting command are different from the third fixed codes in a state in which the second pre-test entry signal is enabled; and

a reset signal enable section configured to enable the reset signal when even any one of the first and second reset enable signals is enabled or another command other than the test setting command is inputted.

5. The semiconductor apparatus according to claim 4, wherein the test entry signal generation block enables the first pre-test entry signal when the first trigger signal is enabled, enables the second pre-test entry signal when the second trigger signal is enabled in a state in which the first pre-test entry signal is enabled, and enables the test entry signal when the third trigger signal is enabled in a state in which the second pre-test entry signal is enabled.

6. The semiconductor apparatus according to claim 5, wherein the test entry signal generation block disables the first and second pre-test entry signals and the test entry signal in response to the reset signal.

7. The semiconductor apparatus according to claim 1, wherein the test entry control block selectively enables the plurality of trigger signals when the test setting command and the addresses with pluralities of predetermined values are inputted.

8. The semiconductor apparatus according to claim 7, wherein the test entry control block enables a reset signal when a normal command other than the test setting command is inputted.

9. The semiconductor apparatus according to claim 8, wherein the test entry control block enables the reset signal when the addresses are not the predetermined values while the test setting command and the addresses are inputted.

10. The semiconductor apparatus according to claim 9, wherein the test entry signal generation block is initialized when the reset signal is enabled while the plurality of trigger signals are sequentially enabled.