Techniques to communicate with a controller for a non-volatile dual in-line memory module

• US 9,645,829 B2
• Filed: 06/30/2014
• Issued: 05/09/2017
• Est. Priority Date: 06/30/2014
• Status: Active Grant

• Current Assignee: SK Hynix NAND Product Solutions Corporation (SK Hynix Inc.)
• Original Assignee: Intel Corporation
• Inventors: Jayakumar, Sarathy, Kumar, Mohan J., Brooks, Adam J., Vergis, George
• Primary Examiner(s): Iqbal, Nadeem
• Application Number:
  US14/319,361
• Publication Number:
  US 20150378841A1
• Time in Patent Office: 1,044 Days
• CPC Class Codes: G06F 11/1441 Resetting or repowering
• CPC Class Codes: G06F 11/2015 Redundant power supplies power supply failure G06F1/30
• CPC Class Codes: G06F 9/4401 Bootstrapping security arrangements therefor G06F21/57

Abstract

Examples may include communicating with a controller for a non-volatile dual in-line memory module through a system management bus (SMBus) interface. In some examples, selective assertion of bits maintained in registers accessible through the SMBus interface may enable communication with the controller. The selective assertion may be based on a register map.

Claims

1. An apparatus comprising:

circuitry at a controller for a non-volatile memory capable of preserving data maintained in volatile memory, the non-volatile and the volatile memory resident on a non-volatile dual in-line memory module (NVDIMM), the NVDIMM comprising a first set of registers, a second set of registers, and a third set of registers;

a receive component for execution by the circuitry to receive a status request and a first command, the first command to be received via assertion of a first set of bits maintained in the first set of registers, the assertion of the first set of bits based on a register map;

a status component for execution by the circuitry to determine a status responsive to the status request; and

an indicate component for execution by the circuitry to indicate the status via selective assertion of a second set of bits maintained in the second set of registers and to indicate acceptance and completion status of the first command via assertion of a third set of bits maintained in a third set of registers of the NVDIMM, the selective assertion based on the register map and the assertion of the third set of bits based on the register map.

2. The apparatus of claim 1, the first set of registers accessible to a requestor of the status request through a system management bus (SMBus) interface.

3. The apparatus of claim 2, the requester comprising a basic input/output system (BIOS), an application or a device driver implemented by host circuitry at a host computing platform coupled with the NVDIMM, the status request including at least one of a request for a health status of the NVDIMM, a request for a state of the controller or a request for a state of the NVDIMM.

4. The apparatus of claim 3, comprising the indicate component to indicate the status as at least one of a busy controller, a not busy controller, a save in progress, an abort save in progress, a restore in progress, an abort restore in progress, an erase in progress, an abort erase in progress, save pin not asserted on a previous start-up or boot of the NVDIMM, save pin asserted on a previous start-up or boot of the NVDIMM that triggered a catastrophic save, catastrophic save successful or catastrophic save not successful.

5. The apparatus of claim 2, the second set of registers accessible to the requestor through the SMBus interface and the third set of registers accessible to the requestor through the SMBus interface.

6. The apparatus of claim 5, comprising the indicate component to indicate a first completion status of the first command via assertion of a fourth set of bits maintained in a fourth set of registers of the NVDIMM, the assertion of the fourth set of bits based on the register map, the first completion status including a successful completion of the first command or a failure to complete the first command, the fourth set of registers accessible to the requestor through the SMBus interface.

7. The apparatus of claim 6, comprising:

the receive component to receive an abort command from the requestor to abort the first command via assertion of a fifth set of bits maintained in a fifth set of registers of the NVDIMM, the assertion of the fifth set of bits based on the register map, the fifth set of registers accessible to the requestor through the SMBus interface; and

the indicate component to indicate acceptance of the abort command and subsequent completion of the abort command via assertion of a sixth set of bits maintained in a sixth set of registers of the NVDIMM, the assertion of the sixth set of bits based on the register map, the sixth set of registers accessible to the requestor through the SMBus interface.

8. The apparatus of claim 6, comprising:

the first command is a save command to preserve data maintained in the volatile memory at a given point in time; and

a save component for execution by the circuitry to save the data in a first region of the non-volatile memory and maintain an association between a first global unique identifier (GUID) indicated by the requestor, the GUID indicated with the save command.

9. The apparatus of claim 6, comprising:

the first command is a restore command to restore data saved in the non-volatile memory to the volatile memory; and

a restore component for execution by the circuitry to restore the data from a first region of the non-volatile memory, the first region previously associated with a first global unique identifier (GUID) indicated by the requestor, the GUID indicated with the restore command.

10. The apparatus of claim 6, comprising:

the first command is an erase command to erase data saved in the non-volatile memory; and

an erase component for execution by the circuitry to erase the data from a first region of the non-volatile memory, the first region previously associated with a first global unique identifier (GUID) indicated by the requestor, the GUID indicated with the erase command.

11. The apparatus of claim 6, comprising:

the first command received by the receive component is an arm command;

an arm component for execution by the circuitry to cause one or more capacitors coupled with the NVDIMM to charge; and

a save component for execution by the circuitry capable of implementing a catastrophic save using power supplied by the one or more capacitors to preserve data maintained in the volatile memory if a direct current power supply loss is sensed or expected.

12. The apparatus of claim 11, comprising:

the receive component to receive a disarm command from the requestor, the disarm command received via assertion of a fifth set of bits maintained in a fifth set of registers of the NVDIMM, the assertion of the fifth set of bits based on the register map, the fifth set of registers accessible to the requestor through the SMBus interface; and

the arm component to allow the one or more capacitors to discharge responsive to the disarm command; and

the indicate component to indicate acceptance of the disarm command and subsequent completion of the disarm command via assertion of a sixth set of bits maintained in a sixth set of registers of the NVDIMM, the assertion of the sixth set of bits based on the register map, the sixth set of registers accessible to the requestor through the SMBus interface.

13. The apparatus of claim 1, the non-volatile memory including NAND flash memory and the volatile memory including dynamic random access memory (DRAM).

14. A method comprising:

receiving, at a controller, a status request, the controller for a non-volatile memory capable of preserving data maintained in volatile memory, the non-volatile and the volatile memory resident on a non-volatile dual in-line memory module (NVDIMM);

determining a status responsive to the status request;

indicating the status via selective assertion of a first set of bits maintained in a first set of registers of the NVDIMM, the selective assertion based on a register map;

receiving, at the controller, a first command via assertion of a second set of bits maintained in a second set of registers of the NVDIMM, the assertion of the second set of bits based on the register map; and

indicating acceptance and completion status of the first command via assertion of a third set of bits maintained in a third set of registers of the NVDIMM, the assertion of the third set of bits based on the register map.

15. The method of claim 14, comprising the first set of registers accessible to a requestor of the status request through a system management bus (SMBus) interface.

16. The method of claim 15, the status request comprising a request for a state of the controller or of the NVDIMM.

17. The method of claim 15, the second set of registers accessible to the requestor through the SMBus interface and the third set of registers accessible to the requestor through the SMBus interface.

18. The method of claim 17, comprising:

indicating a first completion status of the first command via assertion of a fourth set of bits maintained in a fourth set of registers of the NVDIMM, the assertion of the fourth set of bits based on the register map, the first completion status including a successful completion of the first command or a failure to complete the first command, the fourth set of registers accessible to the requestor through the SMBus interface.

19. The method of claim 18, comprising:

receiving an abort command from the requestor to abort the first command via assertion of a fifth set of bits maintained in a fifth set of registers of the NVDIMM, the assertion of the fifth set of bits based on the register map, the fifth set of registers accessible to the requestor through the SMBus interface; and

indicating acceptance of the abort command and subsequent completion of the abort command via assertion of a sixth set of bits maintained in a sixth set of registers of the NVDIMM, the assertion of the sixth set of bits based on the register map, the sixth set of registers accessible to the requestor through the SMBus interface.

20. At least one non-transitory machine readable medium comprising a plurality of instructions that in response to being executed by system at a host computing platform cause the system to:

send a status request to a controller for a non-volatile memory capable of preserving data maintained in volatile memory, the non-volatile and the volatile memory resident on a non-volatile dual in-line memory module (NVDIMM) coupled with the host computing platform;

access a first set of bits maintained in a first set of registers of the NVDIMM through a system management bus (SMBus) interface, the first set of bits indicating a status indicated by the controller responsive to the status request via selective asserting of the first set of bits based on a register map;

send a command via assertion of a second set of bits maintained in a second set of registers of the NVDIMM, the assertion of the second set of bits based on the register map; and

receive an indication of acceptance and completion status of the command via a third set of bits maintained in a third set of registers of the NVDIMM.

21. The at least one non-transitory machine readable medium of claim 20, the status request comprising a request for a state of the controller or of the NVDIMM.

22. The at least one non-transitory machine readable medium of claim 20, the assertion of the second set of bits based on the register map, the second set of registers accessible through the SMBus interface;

and the third set of bits asserted by the controller, based on the register map, the third set of registers accessible through the SMBus interface.

23. A system comprising:

circuitry for a host computing platform to implement a basic input/output system (BIOS), an application or a device driver;

a non-volatile dual in-line memory module (NVDIMM) having resident non-volatile memory and volatile memory, the non-volatile memory capable of preserving data maintained in a volatile memory; and

a controller for the non-volatile memory, the controller operative to;

receive a status request from the BIOS, the application or the device driver, the status request comprising a request for a health status of the NVDIMM, a state of the controller or a state of the NVDIMM;

determine a status responsive to the status request;

indicate the status via selective assertion of a first set of bits maintained in a first set of registers of the NVDIMM, the selective assertion based on a register map; and

receive a command from the BIOS, the application or the device driver via assertion of a second set of bits maintained in a second set of registers of the NVDIMM, the assertion of the second set of bits based on the register map.

24. The system of claim 23, comprising the first set of registers accessible to the BIOS, the application or the device driver through a system management bus (SMBus) interface.

25. The system of claim 24, the second set of registers accessible to the BIOS, the application or the device driver through the SMBus interface, the controller operative to:

indicate acceptance and completion status of the command via assertion of a third set of bits maintained in a third set of registers of the NVDIMM, the assertion of the third set of bits based on the register map, the third set of registers accessible to the BIOS, the application or the device driver through the SMBus interface; and

indicate a completion status of the command via assertion of a fourth set of bits maintained in a fourth set of registers of the NVDIMM, the assertion of the fourth set of bits based on the register map, the completion status including a successful completion of the command or a failure to complete the command, the fourth set of registers accessible to the BIOS, the application or the device driver through the SMBus interface.