Self-aligned flash memory device with word line having reduced height at outer edge opposite to gate stack

• US 9,646,978 B2
• Filed: 06/03/2015
• Issued: 05/09/2017
• Est. Priority Date: 06/03/2015
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Wu, Chang-Ming, Liu, Shih-Chang
• Primary Examiner(s): Smoot, Stephen W
• Application Number:
  US14/729,553
• Publication Number:
  US 20160358928A1
• Time in Patent Office: 706 Days
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/7684 Smoothing; Planarisation
• CPC Class Codes: H01L 21/76883 Post-treatment or after-treatment of the conductive material
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7831 with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645
• CPC Class Codes: H01L 29/788 with floating gate H01L29/78391 takes precedence
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND

Abstract

The present disclosure relates to a flash memory device, and associated methods. In some embodiments, the flash memory device has a gate stack with a control gate separated from a floating gate by a control gate dielectric. An erase gate disposed on a first side of the gate stack. A word line is disposed on a second side of the gate stack that is opposite the first side. The word line has a height that monotonically increases from an outer side opposite to the gate stack to an inner side closer to the gate stack. The shape of the word line optimizes the contact resistance of the word line and allows for an overlying cap spacer formed on the word line to be well defined, which can provide more reliable read/write operations and/or better performance.

Claims

1. A flash memory device, comprising:

a gate stack comprising a control gate separated from a floating gate by a control gate dielectric;

an erase gate disposed on a first side of the gate stack; and

a word line disposed on a second side of the gate stack that is opposite the first side, wherein the word line has a height that monotonically increases from an outer side opposite to the gate stack to an inner side closer to the gate stack;

wherein the word line comprises a ledge at the outer side of the word line with a planar upper surface, and a tilted portion at the inner side of the word line.

2. The flash memory device of claim 1, wherein a slope of a top surface of the tilted portion of the word line decreases from the outer side to the inner side of the tilted portion of the word line.

3. The flash memory device of claim 1, wherein the tilted portion of the word line comprises an upper surface having a slope that decreases as a distance from the gate stack decreases.

4. The flash memory device of claim 1, wherein the erase gate has a planar upper surface.

5. The flash memory device of claim 1, further comprising:

a word line cap spacer disposed on the word line and an erase gate cap spacer disposed on the erase gate; and

a dielectric segment comprising a different material than the word line cap spacer, which is disposed at an upper outer edge of the word line cap spacer.

6. The flash memory device of claim 1, further comprising:

a sidewall spacer disposed along an outer sidewall of the word line;

an interlayer dielectric (ILD) layer arranged over the gate stack, the erase gate and the word line;

silicide pads arranged over the word line and the erase gate; and

conductive contacts extending through the ILD layer to the silicide pads.

7. The flash memory device of claim 1, wherein the gate stack further comprises a hard mask disposed over the control gate.

8. The flash memory device of claim 1, wherein the floating gate has a floating gate ledge comprising a reduced height and surrounding a central region of the floating gate, and wherein the flash memory device further comprises a dielectric cap extending from the floating gate ledge over a top surface of the gate stack.

9. The flash memory device of claim 1, further including:

a second gate stack disposed on an opposite side of the erase gate as the gate stack, wherein the second gate stack comprises a second control gate arranged over a second floating gate; and

a second word line disposed at a second side of the second gate stack as the erase gate, wherein the second word line has a height that monotonically increases from an outer side opposite to the second gate stack to an inner side closer to the second gate stack.

10. The flash memory device of claim 1, wherein the erase gate and the word line share a crystalline structure.

11. An integrated circuit for a flash memory device, comprising:

a common source/drain region shared by a pair of memory cells disposed in a substrate;

a pair of gate stacks disposed at opposite sides of the common source/drain region over the substrate, wherein the pair of gate stacks respectively comprise a floating gate and a control gate arranged over the floating gate;

a pair of word lines disposed at opposite sides of the gate stacks as the common source/drain region, wherein each of the pair of word lines has a height that monotonically increases from an outer side opposite to the gate stacks to an inner side closer to the gate stacks;

a pair of sidewall spacers disposed along outer sidewalls of the word lines;

an erase gate disposed over the common source/drain region between the gate stacks; and

an erase gate cap spacer disposed over the erase gate, wherein an upper surface of the erase gate cap spacer is recessed.

12. The integrated circuit of claim 11, wherein each of the word lines comprises a ledge portion abutting the corresponding sidewall spacer, the ledge portion has a reduced height relative to a top surface of the word lines.

13. The integrated circuit of claim 12, wherein each of the word lines comprises a tilted portion connecting to the ledge portion, wherein a slope of the top surface of the tilted portion of the word lines decreases from the outer side to the inner side of the tilted portion of the word lines.

14. The integrated circuit of claim 11, further comprising:

word line cap spacers disposed over the word lines and abutting upper portions of the sidewall spacers.

15. A flash memory device, comprising:

a gate stack arranged over a substrate and comprising a control gate separated from a floating gate by a control gate dielectric;

a word line disposed on one side of the gate stack wherein the word line has a height that monotonically increases from an outer side opposite to the gate stack to an inner side closer to the gate stack;

a word line cap spacer disposed on the word line, including a ledge locating at an upper outer edge of the word line cap spacer; and

a dielectric segment comprising a different material than the word line cap spacer, which is disposed on the ledge of the word line cap spacer and has an outer sidewall vertically aligned with outer sidewalls of the word line and the word line cap spacer.

16. The flash memory device of claim 15, wherein the word line cap spacer has a concave upper surface, such that a height of the word line cap spacer from the concave upper surface to a surface of the substrate monotonically decreases from a peripheral region to a middle region.

17. The flash memory device of claim 15, wherein the dielectric segment comprised nitride and the word line cap spacer comprises oxide.

18. The flash memory device of claim 15, further comprising:

an erase gate disposed on a side of the gate stack opposite to the word line;

wherein the erase gate comprises a planar upper surface.

19. The flash memory device of claim 18, further comprising:

an erase gate cap spacer disposed on the erase gate;

wherein the erase gate cap spacer has a concave upper surface such that a height of the erase gate cap spacer from the concave upper surface to a surface of the substrate monotonically decreases from a peripheral region to a middle region.

20. A flash memory device, comprising:

a gate stack comprising a control gate separated from a floating gate by a control gate dielectric;

an erase gate disposed on a first side of the gate stack; and

a word line disposed on a second side of the gate stack that is opposite the first side, wherein the word line has a ledge portion at an outer side opposite to the gate stack and surrounding a tilted portion at an inner side closer to the gate stack;

wherein the ledge portion has a planar upper surface and a reduced height smaller than a height of the tilted portion at the inner side of the word line.