Thermionically-overdriven tunnel FETs and methods of fabricating the same

• US 9,647,098 B2
• Filed: 01/09/2015
• Issued: 05/09/2017
• Est. Priority Date: 07/21/2014
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Obradovic, Borna, Bowen, Robert C., Palle, Dharmendar Reddy, Rodder, Mark S.
• Primary Examiner(s): GONDARENKO, NATALIA A
• Application Number:
  US14/593,636
• Publication Number:
  US 20160020305A1
• Time in Patent Office: 851 Days
• Field of Search: 438448, 257314, 257315, 257105, 257 30, 257 39, 257104, 257E29024, 257E29168, 36518512
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/8252 the substrate being a semiconductor, using III-V technology H01L21/8258 takes precedence
• CPC Class Codes: H01L 27/0605 integrated circuits made of compound material, e.g. AIIIBV
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/20 including, apart from doping materials or other impurities, only AIIIBV compounds
• CPC Class Codes: H01L 29/205 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66977 Quantum effect devices, e.g. using quantum reflection, diffraction or interference effects, i.e. Bragg- or Aharonov-Bohm effects
• CPC Class Codes: H01L 29/7391 Gated diode structures

Abstract

A field effect transistor (FET) includes a nanosheet stack having first and second stacked semiconductor channel layers. The first channel layer defines a channel region of a tunnel FET, and the second channel layer defines a channel region of a thermionic FET. Source and drain regions are provided on opposite sides of the nanosheet stack such that the first and second channel layers extend therebetween. A first portion of the source region adjacent the first channel layer and a second portion of the source region adjacent the second channel layer have opposite semiconductor conductivity types. Related fabrication and operating methods are also discussed.

Claims

1. A field effect transistor (FET), comprising:

a nanosheet stack comprising first and second semiconductor channel layers that are stacked in a first direction, the first channel layer defining a channel region of a tunnel FET, and the second channel layer defining a channel region of a thermionic FET; and

source and drain regions on opposite sides of the nanosheet stack such that the first and second channel layers extend therebetween, wherein a first portion of the source region directly adjoining the first channel layer and a second portion of the source region directly adjoining the second channel layer have opposite semiconductor conductivity types, wherein a third portion of the source region distal from both the first and second channel layers comprises a p-n junction within the third portion of the source region at an interface between semiconductor portions of the opposite semiconductor conductivity types, wherein the p-n junction is distal from the first and second channel layers in the nanosheet stack and extends in a second direction that is different than the first direction.

2. The transistor of claim 1, wherein the nanosheet stack further comprises respective gate layers on opposing surfaces of the first and second channel layers, and respective gate dielectric layers between the gate layers and the first and second channel layers, wherein the p-n junction does not extend between the respective gate layers.

3. The transistor of claim 2, wherein a threshold voltage of the tunnel FET is less than a threshold voltage of the thermionic FET, and wherein, responsive to application of the threshold voltage of the thermionic FET to the respective gate layers on the opposing surfaces of the first and second channel layers, conduction in the channel region of the thermionic FET is substantially greater than conduction in the channel region of the tunnel FET.

4. The transistor of claim 3, wherein:

the first and second channel layers are both n-channel layers or are both p-channel layers;

the first and second channel layers extend in the second direction, which is perpendicular to the first direction; and

the first and second channel layers comprise different dopant concentrations, different thicknesses, or different dopant concentrations and different thicknesses.

5. The transistor of claim 4, wherein a thickness of the first channel layer is sufficient to prevent band-to-band tunneling in the first channel layer at the drain region at gate voltages greater than the threshold voltage of the thermionic FET.

6. The transistor of claim 5, wherein a thickness of the second channel layer is greater than the thickness of the first channel layer.

7. The transistor of claim 3, wherein the nanosheet stack comprises a plurality of first and second channel layers, wherein respective spacings between the first channel layers of the plurality of first and second channel layers differ from respective spacings between the second channel layers of the plurality of first and second channel layers.

8. The transistor of claim 1, wherein the first and second portions of the source region comprise respective doped extension regions at opposite ends of the first and second channel layers adjacent the source and drain regions and extending between the gate layers.

9. The transistor of claim 8, further comprising:

respective dielectric suspension regions separating ends of the gate layers from the source and drain regions,

wherein the doped extension regions laterally extend from the source and drain regions to the first and second channel layers between the gate layers and adjacent the dielectric suspension regions.

10. The transistor of claim 2, further comprising:

respective contacts on the source and drain regions, wherein one of the respective contacts on the source region electrically connects the first and second portions of the source region having the opposite conductivity types to provide an electrical short across the p-n junction.

11. The transistor of claim 1, wherein the first and second channel layers comprise different semiconductor materials or different compositions of a same semiconductor material.

12. The transistor of claim 11, wherein at least one of the first and second channel layers comprises Group III-V semiconductor materials or Group IV semiconductor materials.

13. The transistor of claim 12, wherein the Group III-V semiconductor materials comprise at least one selected from a group consisting of indium gallium arsenide (InGaAs), indium arsenide (InAs), indium antimonide (InSb), and indium gallium antimonide (InGaSb), and wherein the Group IV semiconductor materials comprise silicon (Si), germanium (Ge), and silicon germanium (SiGe).

14. The transistor of claim 2, wherein the first and second channel layers and the source and drain regions comprise epitaxial layers.

15. The transistor of claim 14, wherein the nanosheet stack comprises a heteroepitaxial stack comprising crystalline semiconductor first and second channel layers, crystalline semiconductor gate layers, and crystalline semiconductor or insulating gate dielectric layers, wherein respective interfaces between the first and second channel layers and the gate dielectric layers are free of non-crystalline materials.

16. A method of fabricating a field effect transistor (FET), the method comprising:

providing a nanosheet stack comprising first and second semiconductor channel layers that are stacked in a first direction, the first channel layer defining a channel region of a tunnel FET, and the second channel layer defining a channel region of a thermionic FET; and

forming source and drain regions on opposite sides of the nanosheet stack such that the first and second channel layers extend therebetween,

wherein a first portion of the source region directly adjoining the first channel layer and a second portion of the source region directly adjoining the second channel layer have opposite semiconductor conductivity types, wherein a third portion of the source region distal from both the first and second channel layers comprises a p-n junction within the third portion of the source region at an interface between semiconductor portions of the opposite semiconductor conductivity types, wherein the p-n junction is distal from the first and second channel layers in the nanosheet stack and extends in a second direction that is different than the first direction.

17. The method of claim 16, wherein a threshold voltage of the tunnel FET is less than a threshold voltage of the thermionic FET, and wherein providing the nanosheet stack further comprises:

forming respective gate dielectric layers on opposing surfaces of the first and second channel layers; and

forming gate layers on the gate dielectric layers,

wherein the p-n junction does not extend between the gate layers.

18. The method of claim 17, wherein providing the nanosheet stack further comprises:

forming the first and second channel layers comprising different dopant concentrations, different thicknesses, or different dopant concentrations and different thicknesses,

wherein the first and second channel layers are both n-channel layers or are both p-channel layers, and wherein the first and second channel layers extend in the second direction, which is perpendicular to the first direction.

19. The method of claim 18, wherein the first channel layer is formed to a thickness sufficient to prevent band-to-band tunneling therein at the drain region at gate voltages greater than the threshold voltage of the thermionic FET, and wherein the second channel layer is formed to a thickness greater than the thickness of the first channel layer.

20. The method of claim 16, wherein the first and second channel layers and the source and drain regions comprise epitaxial layers.

21. A method of operating a field-effect transistor (FET), the method comprising:

applying a first supply voltage to a gate electrode extending between first and second semiconductor channel layers in a first operating mode, the first and second channel layers being stacked in a first direction and extending between a drain region and a source region, the source region including first and second portions of opposite semiconductor conductivity types directly adjoining the first and second channel layers, respectively, and a third portion distal from both the first and second channel layers that comprises a p-n junction within the third portion of the source region at an interface between semiconductor portions of the opposite semiconductor conductivity types, wherein the p-n junction is distal from the first and second semiconductor channel layers and extends in a second direction that is different than the first direction, and wherein the first supply voltage is sufficient to cause conduction in the first channel layer but is insufficient to cause significant conduction in the second channel layer; and

applying a second supply voltage to the gate electrode in a second operating mode, wherein the second supply voltage is sufficient to cause conduction in the second channel layer that is substantially greater than the conduction in the first channel layer, wherein the first channel layer defines a channel region of a tunnel FET, and wherein the second channel layer defines a channel region of a thermionic FET.

22. The method of claim 21, wherein the first and second channel layers extend in the second direction, which is perpendicular to the first direction, wherein the first and second channel layers are both n-channel layers or are both p-channel layers, and wherein the thermionic FET has a threshold voltage greater than a threshold voltage of the tunnel FET.

23. The method of claim 22, wherein the respective threshold voltages provide a substantially same off-state leakage for the tunnel FET and the thermionic FET in the first and second operating modes, respectively.

24. The method of claim 23, wherein a thickness of the first channel layer is sufficient to prevent band-to-band tunneling in the first channel layer at the drain region responsive to application of the second supply voltage to the gate electrode in the second operating mode.